Xilinx UG144 manual Implementing Your Design, Pre-implementation Simulation, Synthesis

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Chapter 12

Implementing Your Design

This chapter describes how to simulate and implement your design containing the

GEMAC core.

Pre-implementation Simulation

A unit delay structural model of the GEMAC core netlist is provided as a CORE Generator™ output file. This can be used for simulation of the block in the design phase of the project.

Using the Simulation Model

For information about setting up your simulator to use the pre-implemented model, see the Xilinx Synthesis and Verification Design Guide, included in your Xilinx software installation.

The unit delay structural model of the GEMAC core can be found in the CORE Generator project directory. Details of the CORE Generator outputs can be found in the 1-Gigabit Ethernet MAC Getting Started Guide.

VHDL

•<component_name>.vhd

Verilog

•<component_name>.v

Synthesis

XST—VHDL

Acomponent and instantiation template for the core named <component_name>.vho is provided in the CORE Generator project directory. Use this to help instance the GEMAC core into your VHDL source.

After your entire design is complete, create:

•An XST project file top_level_module_name.prj listing all the user source code files.

•An XST script file top_level_module_name.scr containing your required synthesis options.

1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com 123

UG144 April 24, 2009