R

-- DISCONTINUED PRODUCT --

Chapter 5: Using the Client Side Data Path

Address Filter

If the optional Address Filter is included in the core, the MAC is able to reject frames that do not contain a known address in their destination address field. If a frame is rejected, the rx_data_valid signal is not asserted for the duration of the frame. In addition, neither rx_good_frame or rx_bad_frame are asserted at the end of the frame. The statistics vectors are still output with a valid pulse at the end of the rejected frame.

If the Address Filter is not in promiscuous mode, it will reject frames in which the destination address does not meet any of the following criteria:

It is equal to the broadcast address defined in the IEEE 802.3-2005specification.

It is equal to the pause multicast address defined in the IEEE 802.3-2005specification.

The destination address field contains the pause frame MAC source address specified in the Receiver Configuration Word 0 and Word 1.

It is equal to the MAC unicast address. When the optional Management Interface is present, this is found in the unicast address configuration registers (Table 8-8and Table 8-9, page 82). If the Management Interface is not present the unicast address is input on the mac_unicast_address input.

It matches any of the addresses stored in the MAC address table. The address table is only present when the MAC contains the optional Management Interface and the core was built with one or more address table entries.

Receiver Statistics Vector

The statistics for the frame received are contained within the rx_statistics_vector. The vector is driven synchronously by the receiver clock, gmii_rx_clk, following frame reception. The bit field definition for the vector is defined in Table 5-2.

All bit fields, with the exception of byte valid, are valid only when the

rx_statistics_valid is asserted. This is illustrated in Figure 5-5. Byte valid is significant on every gmii_rx_clk cycle.

Caution! The statistic vectors in this release have been made compatible with the Tri-Mode

Ethernet MAC core. They are not backwards compatible with previous versions of the 1-Gigabit

Ethernet MAC core (see Table 5-3for Receiver Statistic Vector conversion details)

gmii_rx_clk

rx_statistics_valid

rx_statistics_vector[27:0]

Figure 5-5:Receiver Statistics Vector Timing

44

www.xilinx.com

1-Gigabit Ethernet MAC v8.5 User Guide

 

 

UG144 April 24, 2009

Page 44
Image 44
Xilinx UG144 manual 5Receiver Statistics Vector Timing

UG144 specifications

The Xilinx UG144, a comprehensive user guide for the versatile Zynq-7000 SoC (System on Chip) architecture, serves as an essential resource for developers and engineers designing embedded systems. Emphasizing the blend of programmable logic and processing power, this guide highlights the array of features and technologies that make the Zynq-7000 series particularly attractive for a wide range of applications.

One of the standout characteristics of the Zynq-7000 is its dual-core ARM Cortex-A9 processor, which delivers substantial performance for complex processing tasks. This soft processor enables high-speed computation, making it ideal for applications in fields such as automotive, industrial automation, and telecommunications. The guide emphasizes the ability to run multiple operating systems, including Linux and real-time operating systems, providing developers with versatile options for application design.

Additionally, the Xilinx UG144 outlines the extensive programmable logic resources integrated within the Zynq-7000 device. This FPGA fabric allows for customization and parallel processing capabilities, allowing designers to create powerful hardware accelerators tailored to specific application needs. The guide details how these programmable logic resources can easily interface with the ARM processors through a high-bandwidth AXI interface, promoting efficient data flow between the hardware and software components.

Key features highlighted in the UG144 include advanced connectivity options, including PCIe, USB, and Serial interfaces, which facilitate communication with other devices and systems. Furthermore, the guide provides insights into the supported design tools, such as the Xilinx Vivado Design Suite, which aids in both hardware and software co-design. This integrated environment significantly reduces development time while providing an efficient workflow for prototyping and testing.

In terms of performance optimizations, the guide discusses support for digital signal processing (DSP) capabilities, making the Zynq-7000 suitable for high-performance applications such as video processing and data analytics. The built-in DSP slices allow for efficient execution of complex mathematical functions, which is crucial for real-time data processing tasks.

Overall, the Xilinx UG144 guide encapsulates the versatility, performance, and flexibility of the Zynq-7000 SoC architecture. With its combination of ARM processing and programmable logic, along with robust connectivity options and development tools, it empowers engineers to create innovative solutions across a spectrum of industries, solidifying Xilinx's position as a leader in the field of embedded system design.