-- DISCONTINUED PRODUCT --

Receiving Inbound Frames

Table 5-2:Bit Definition for the Receiver Statistics Vector

R

rx_statistics_vector

Name

Description

bit(s)

 

 

 

 

 

27

Address Match

If the optional Address Filter is included in the

 

 

core, this bit is asserted if the address of the

 

 

incoming frame matches one of the stored or

 

 

pre-set addresses in the Address Filter. If the

 

 

Address Filter is omitted from the core, or is

 

 

configured in promiscuous mode, this line is

 

 

held high.

 

 

 

26

Reserved

Always at logic 0.

 

 

 

25

Length/Type

If the length/type field contained a length

 

Out of Range

value that did not match the number of MAC

 

 

client data bytes received and the length/type

 

 

field checks are enabled, then this bit is

 

 

asserted.

 

 

This bit is also asserted if the length/type field

 

 

is less than 46 and the frame is not padded to

 

 

exactly 64 bytes. This is independent of

 

 

whether or not the length/type field checks

 

 

are enabled.

 

 

 

24

Bad Opcode

Asserted if the previous frame was error-free

 

 

and contained the special control frame

 

 

identifier in the length/type field, but

 

 

contained an opcode that is unsupported by

 

 

the MAC (any opcode other than Pause).

 

 

 

23

Flow Control

Asserted if the previous frame met all the

 

Frame

following conditions:

 

 

error-free

 

 

• contained the special control frame

 

 

identifier in the length/type field

 

 

• contained a destination address that

 

 

matched either the MAC Control Multicast

 

 

Address or the configured source address

 

 

of the MAC

 

 

• contained the supported Pause opcode

 

 

• was acted upon by the MAC

 

 

 

22

Byte Valid

Asserted if a MAC frame byte (DA to FCS

 

 

inclusive) is in the process of being received.

 

 

This is valid on every clock cycle.

 

 

Do not use this as an enable signal to indicate

 

 

that data is present on rx_data.

 

 

 

21

VLAN frame

Asserted if the previous frame contained a

 

 

VLAN identifier in the length/type field when

 

 

receiver VLAN operation is enabled.

 

 

 

1-Gigabit Ethernet MAC v8.5 User Guide

www.xilinx.com

45

UG144 April 24, 2009

Page 45
Image 45
Xilinx UG144 manual DIS Product

UG144 specifications

The Xilinx UG144, a comprehensive user guide for the versatile Zynq-7000 SoC (System on Chip) architecture, serves as an essential resource for developers and engineers designing embedded systems. Emphasizing the blend of programmable logic and processing power, this guide highlights the array of features and technologies that make the Zynq-7000 series particularly attractive for a wide range of applications.

One of the standout characteristics of the Zynq-7000 is its dual-core ARM Cortex-A9 processor, which delivers substantial performance for complex processing tasks. This soft processor enables high-speed computation, making it ideal for applications in fields such as automotive, industrial automation, and telecommunications. The guide emphasizes the ability to run multiple operating systems, including Linux and real-time operating systems, providing developers with versatile options for application design.

Additionally, the Xilinx UG144 outlines the extensive programmable logic resources integrated within the Zynq-7000 device. This FPGA fabric allows for customization and parallel processing capabilities, allowing designers to create powerful hardware accelerators tailored to specific application needs. The guide details how these programmable logic resources can easily interface with the ARM processors through a high-bandwidth AXI interface, promoting efficient data flow between the hardware and software components.

Key features highlighted in the UG144 include advanced connectivity options, including PCIe, USB, and Serial interfaces, which facilitate communication with other devices and systems. Furthermore, the guide provides insights into the supported design tools, such as the Xilinx Vivado Design Suite, which aids in both hardware and software co-design. This integrated environment significantly reduces development time while providing an efficient workflow for prototyping and testing.

In terms of performance optimizations, the guide discusses support for digital signal processing (DSP) capabilities, making the Zynq-7000 suitable for high-performance applications such as video processing and data analytics. The built-in DSP slices allow for efficient execution of complex mathematical functions, which is crucial for real-time data processing tasks.

Overall, the Xilinx UG144 guide encapsulates the versatility, performance, and flexibility of the Zynq-7000 SoC architecture. With its combination of ARM processing and programmable logic, along with robust connectivity options and development tools, it empowers engineers to create innovative solutions across a spectrum of industries, solidifying Xilinx's position as a leader in the field of embedded system design.