Xilinx UG144 manual Spartan-3, Spartan-3E, Spartan-3A, and Virtex-4 Devices

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Required Constraints

R

INST "rgmii_rxd<?>" TNM = IN_RGMII;

INST "rgmii_rx_ctl" TNM = IN_RGMII;

TIMEGRP "DDR_RISING" = FFS;

TIMEGRP "DDR_FALLING" = FALLING FFS;

TIMEGRP "IN_RGMII" OFFSET = IN 1.1 ns VALID 2.2 ns BEFORE "rgmii_rxc" TIMEGRP "DDR_RISING";

TIMEGRP "IN_RGMII" OFFSET = IN -2.9 ns VALID 2.2 ns BEFORE "rgmii_rxc" TIMEGRP "DDR_FALLING"

The constraints defined in the preceding lines have a built in 10% tolerance: this allows all combinations of the example designs to pass timing. However, these should be tightened in a real customer design as per the following syntax. Manual adjustments to IDELAY values or DCM phase shift requirements may be required to meet these constraints (see the following family specific sections for details).

TIMEGRP "IN_RGMII" OFFSET = IN 1 ns VALID 2 ns BEFORE "rgmii_rxc" TIMEGRP "DDR_RISING";

TIMEGRP "IN_RGMII" OFFSET = IN -3 ns VALID 2 ns BEFORE "rgmii_rxc" TIMEGRP "DDR_FALLING"

Spartan-3, Spartan-3E, Spartan-3A, and Virtex-4 Devices

The RGMII design uses a DCM on the receiver clock domain for all devices except Virtex-

5.Phase-shifting is then applied to the DCM to align the resultant clock so that it will correctly sample the 2 ns RGMII data valid window at the input flip-flops.

The fixed phase-shift is applied to the DCM using the following UCF syntax.

INST *rgmii_interface/rgmii_rxc_dcm CLKOUT_PHASE_SHIFT = FIXED;

INST *rgmii_interface/rgmii_rxc_dcm PHASE_SHIFT = 40;

The value of PHASE_SHIFT is preconfigured in the example designs to meet the setup and hold constraints for the example RGMII pinout in the particular device. The setup/hold timing which is achieved after place-and-route is reported in the data sheet section of the TRCE report (created by the implement script).

For customers fixing their own pinout, the setup and hold figures reported in the TRCE report can be used to initially setup the approximate DCM phase-shift. Appendix C, “Calculating DCM Phase-Shifting”describes a more accurate method for fixing the phase- shift by using hardware measurement of a unique PCB design.

Virtex-5 Devices

The RGMII design uses IODELAY components on both the receiver and transmitter clock domains for Virtex-5 devices. A fixed tap delay is applied to the rgmii_txc output clock to move the rising edge of this clock to the centre of the output data window. For the receiver clock, data and control signals, a fixed tap delay can be applied to either delay the data and control signals or delay the clock so that the data/control are correctly sampled by the rgmii_rxc clock at the IOB IDDR registers, meeting RGMII setup and hold timing.

The choice of delaying data/control or clock is dependant upon a number of factors, not least being the required shift. There are trade-offs to be made with either choice. Delaying the clock is clock-period specific as we move the clock to line up each edge with data from the following edge. Delaying the data/control introduces more jitter which degrades the overall setup/hold window. The interface timing report in the two cases is also quite different. See “Understanding Timing Reports for RGMII Setup/Hold timing.”

The following constraint shows an example of setting the delay value for two of these IODELAY components. Data/Control bits can be adjusted individually to compensate for any PCB routing skew, if desired.

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UG144 April 24, 2009