Configuration Miim access Statistics Read

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The management interfaces of the two cores can be shared by avoiding bus conflict, as follows:

•Selecting a different address range for the statistics to that of the MAC configuration registers. This is achieved by setting host_addr[9] to logic 0 when reading from the statistics and logic 1 when writing and reading to the MAC configuration registers.

•Using the host_miim_sel signal to differentiate between a statistical counter read and a MAC initiated MDIO transaction. This is achieved by setting host_miim_sel to logic 0 for a statistical counter read and logic 1 for a MAC initiated MDIO transaction.

Table 11-1describes the type of host transactions that occur if the host interface is shared (as illustrated in Figure 11-5).

Table 11-1:Management Interface Transaction Types

Transaction	host_miim_sel	host_addr[9]

Configuration	0	1

MIIM access	1	X

Statistics Read	0	0

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UG144 April 24, 2009

UG144 specifications

The Xilinx UG144, a comprehensive user guide for the versatile Zynq-7000 SoC (System on Chip) architecture, serves as an essential resource for developers and engineers designing embedded systems. Emphasizing the blend of programmable logic and processing power, this guide highlights the array of features and technologies that make the Zynq-7000 series particularly attractive for a wide range of applications.

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Xilinx UG144 manual Configuration Miim access Statistics Read

Models: UG144

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Ethernet Statistics Core

Configuration

MIIM access

Statistics Read

UG144 specifications