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Xilinx UG144 manual Receiver Configuration, Using the Optional Management Interface

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Using the Optional Management Interface

R

Receiver Configuration

The register contents for the two receiver configuration words are shown in Table 8-3and Table 8-4.

Table 8-3:Receiver Configuration Word 0

	Bit	Default	Description
	Bit	Value	Description
		Value

	31-0	All 0s	Pause frame MAC Source Address[31:0]. This address is
			used by the MAC to match against the destination address
			of any incoming flow control frames. It is also used by the
			flow control block as the source address (SA) for any
			outbound flow control frames. See Chapter 6, “Using Flow
			Control.”
			The address is ordered so the first byte
			transmitted/received is the lowest positioned byte in the
			register; for example, a MAC address of AA-BB-CC-DD-
			EE-FF would be stored in Address[47:0] as
			0xFFEEDDCCBBAA.

	Table 8-4:Receiver Configuration Word 1

	Bit	Default	Description
	Bit	Value	Description
		Value

	15-0	All 0s	Pause frame MAC Source Address[47:32]

	23-16	n/a	Reserved

	24	0	Control Frame Length Check Disable When this bit is set
			to ‘1,’ the core will not mark control frames as ‘bad’ if they
			are greater than the minimum frame length.

	25	0	Length/Type Error Check Disable When this bit is set to
			‘1,’ the core will not perform the length/type field error
			checks as described in “Length/Type Field Error Checks,”
			on page 43. When this bit is set to ‘0,’ the length/type field
			checks will be performed; this is normal operation.

	26	n/a	Reserved

	27	0	VLAN Enable When this bit is set to ‘1,’ VLAN tagged
			frames will be accepted by the receiver.

	28	1	Receiver Enable. If set to ‘1,’ the receiver block will be
			operational. If set to ‘0,’ the block will ignore activity on the
			physical interface RX port.

1-Gigabit Ethernet MAC v8.5 User Guide

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UG144 April 24, 2009

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Xilinx UG144 manual Using the Optional Management Interface, Receiver Configuration Word, Bit Default Description

Contents

UG144 April 24 LogiCORE IP Gigabit Ethernet MACGigabit Ethernet MAC v8.5 User Guide Date Version Revision Revision HistoryDIS Product Table of Contents Designing with the Core Configuration and Status Appendix C Calculating DCM Phase-Shifting Schedule of Figures 1Block Diagram2External Gmii Receiver Logic for Spartan-3, Spartan-3E, Figure A-2Frame Transfer across LocalLink Interface DIS Product Schedule of Tables Clocking and Resetting Interfacing to Other Cores About This Guide Guide ContentsConvention Meaning or Use Example ConventionsTypographical Preface About This GuideAcronym Spelled Out Online DocumentList of Acronyms ConventionsVhdl Preface About This Guide Acronym Spelled OutRecommended Design Experience Related Xilinx Ethernet Products and ServicesIntroduction About the CoreGemac Core SpecificationsTechnical Support FeedbackSystem Overview Core ArchitectureCore Components Gmac Core with Optional Management Interface Core InterfacesCore Interfaces Core Architecture Core Interfaces Transmitter Interface Client Side InterfaceFlow Control Interface Receiver InterfaceMAC Unicast Address Optional Management Interface OptionalPhysical Side Interface Configuration Vector OptionalAsynchronous Reset 7Reset Signal Direction Clock Domain DescriptionMdio Interface Graphical User Interface Generating the CoreParameter Values in the XCO File Output Generation Generating the Core Design Steps Using the Example Design as a Starting PointDesigning with the Core General Design Guidelines11-Gigabit Ethernet MAC Core Example Design Designing with the CoreImplementing the 1-Gigabit Ethernet MAC in Your Application Know the Degree of DifficultyGeneral Design Guidelines Make Only Allowed Modifications Recognize Timing Critical SignalsKeep it Registered Use Supported Design FlowsNormal Frame Reception Using the Client Side Data Path1Abbreviations Used in Timing Diagrams Definition Receiving Inbound FramesRxgoodframe, rxbadframe timing Using the Client Side Data PathReceiving Inbound Frames Frame Reception with ErrorsVlan Tagged Frames Client-Supplied FCS PassingMaximum Permitted Frame Length Length/Type Field Error ChecksEnabled Disabled5Receiver Statistics Vector Timing Receiver Statistics VectorDIS Product Length see Maximum Permitted Frame Transmitting Outbound Frames Transmitting Outbound FramesNormal Frame Transmission Padding7Frame Transmission with Client-supplied FCS Client Underrun9Transmission of a Vlan Tagged Frame Inter-Frame Gap AdjustmentTransmitter Statistics Vector 10Inter-Frame Gap AdjustmentName Bit 31 is equivalent to bit Overview of Flow Control Using Flow ControlFlow Control Requirement Flow Control Basics Using Flow ControlOverview of Flow Control Pause Control FramesClient Initiated Pause Request Flow Control Operation of the GemacTransmitting a Pause Control Frame Core-initiated Pause RequestFlow Control Operation of the Gemac Receiving a Pause Control FrameCore Initiated Response to a Pause Request Client Initiated Response to a Pause RequestMethod Flow Control Implementation Example4Flow Control Implementation Triggered from Fifo Occupancy Flow Control Implementation ExampleUsing Flow Control Implementing External Gmii Using the Physical Side InterfaceGmii Transmitter Logic 1External Gmii Transmitter Logic Using the Physical Side InterfaceSpartan-3, Spartan-3E, Spartan-3A and Virtex-4 Devices Gmii Receiver LogicImplementing External Gmii DCM Reset circuitry 3External Gmii Receiver Logic for Virtex-5 Devices Virtex-5 DevicesRgmii Transmitter Logic Implementing External RgmiiImplementing External Rgmii Virtex-4 Devices5External Rgmii Transmitter Logic in Virtex-4 Devices 6External Rgmii Transmitter Logic in Virtex-5 Devices Rgmii Receiver Logic 7External Rgmii Receiver Logic Virtex-4 Devices 8External Rgmii Receiver Logic for Virtex-4 Devices 9External Rgmii Receiver Logic for Virtex-5 Devices 10RGMII Inband Status Decoding Logic Rgmii Inband Status Decoding LogicConnecting the Mdio to an Internally Integrated PHY Using the Mdio interfaceConnecting the Mdio to an External PHY Using the Optional Management Interface Configuration and StatusHost Clock Frequency Configuration and Status Configuration Registers2Configuration Registers Address Description Receiver Configuration Word Receiver ConfigurationUsing the Optional Management Interface 3Receiver Configuration Word Bit Default DescriptionInterframe Gap Adjust Enable If ‘1,’ the transmitter will Transmitter Configuration6Flow Control Configuration Word Bit Default Description Flow Control ConfigurationAddress Filter Configuration Mdio Configuration12Address Filter Mode Bits Default Description Writing and Reading to and from the Configuration Registers10Address Table Configuration Word Bits Default Description 11 Address Table Configuration Word1Configuration Register Write Timing 3Address Table Write Timing Accessing the Address TableIntroduction to Mdio Mdio Interface5Typical MDIO-managed System Write TransactionRead Transaction Accessing Mdio With Gemac8MDIO Access through Management Interface Pause frame MAC Source Address470 Access without the Management InterfaceTransmitter Interframe Gap Adjust Enable Receive Flow Control Enable . When this bit Required Constraints Constraining the CoreConstraining the Core Period Constraints for Clock NetsRequired Constraints Timespecs for Critical Logic within the CoreTimespecs for Reset Logic within the Core Constraints when Implementing an External GmiiGmii IOB Constraints 1Input Gmii Timing Symbol Min Max Units Gmii Input Setup/Hold TimingVirtex-5 Devices Virtex-5 devices with Delayed Data/Control Understanding Timing Reports for Gmii Setup/Hold TimingNon-Virtex-5 devices Virtex-5 Devices with Delayed Clock Rgmii IOB Constraints Constraints when Implementing an External Rgmii2Input Rgmii Timing Symbol Min Typical Units Rgmii Input Setup/Hold TimingSpartan-3, Spartan-3E, Spartan-3A, and Virtex-4 Devices Rgmii DDR Constraints Understanding Timing Reports for Rgmii Setup/Hold timing 106 4Timing Report Setup/Hold Illustration 108 With External Gmii Clocking and ResettingClocking the Core With Internal GmiiStandard Clocking Scheme Clocking and ResettingMultiple Cores With Rgmii3Clock Management Logic with External Gmii Multiple Cores Multiple Cores4Clock Management Logic with External Rgmii Multiple Cores Reset ConditionsEthernet 1000Base-X PCS/PMA or Sgmii Core Interfacing to Other CoresInterfacing to Other Cores Integration to Provide 1000BASE-X PCS with TBIEthernet 1000Base-X PCS/PMA or Sgmii Core 116 GTP Virtex-5 LXT and SXT DevicesClkdv Virtex-5 FXT DevicesIntegration to Provide Sgmii Functionality Ethernet Statistics CoreEthernet Statistics Core 120 Configuration Miim access Statistics Read 122 Synthesis Using the Simulation ModelImplementing Your Design Pre-implementation SimulationMapping the Design ImplementationXST-Verilog Generating the Xilinx NetlistGenerating a Bitstream Post-Implementation SimulationPlacing-and-Routing the Design Static Timing AnalysisOther Implementation Information Using the ModelGMII/RGMII Using the Client-Side FifoInterfaces Appendix a Using the Client-Side FifoTransmit Fifo Interfaces Receive FifoData Flow Overview of LocalLink InterfaceClock Requirements Functional OperationFunctional Operation User Interface Data Width Conversion Expanding Maximum Frame SizeVerification by Simulation Core Verification, Compliance, and InteroperabilityHardware Verification 134 DCM Phase-Shifting Calculating DCM Phase-ShiftingFinding the Ideal Phase-Shift Appendix C Calculating DCM Phase-Shifting Transmit Path Latency Core LatencyReceive Path Latency Appendix D Core Latency