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Appendix C

Calculating DCM Phase-Shifting

DCM Phase-Shifting

A DCM is used in the receiver clock path to meet the input setup and hold requirements when using the core with an RGMII (see “Implementing External RGMII,” on page 66) and with an external GMII implementation in Spartan®-3, Spartan-3E, Spartan-3A and Virtex®-4 devices (see “Spartan-3,Spartan-3E,Spartan-3A and Virtex-4 Devices,” on page 63.)

In these cases, a fixed phase-shift offset is applied to the receiver clock DCM to skew the clock. This performs static alignment by using the receiver clock DCM to shift the internal version of the receiver clock such that its edges are centered on the data eye at the IOB DDR flip-flops. The ability to shift the internal clock in small increments is critical for sampling high-speed source synchronous signals such as RGMII. For statically aligned systems, the DCM output clock phase offset (as set by the phase shift value) is a critical part of the system, as is the requirement that the PCB is designed with precise delay and impedance- matching for all the GMII/RGMII receiver data bus and control signals.

You must determine the best DCM setting (phase-shift) to ensure that the target system has the maximum system margin to perform across voltage, temperature, and process (multiple chips) variations. Testing the system to determine the best DCM phase-shift setting has the added advantage of providing a benchmark of the system margin based on the UI (unit interval or bit time).

System margin is defined as the following:

System Margin (ps) = UI(ps) * (working phase-shift range/128)

Finding the Ideal Phase-Shift

Xilinx cannot recommend a singular phase-shift value that is effective across all hardware platforms, and does not recommend attempting to determine the phase-shift setting empirically. In addition to the clock-to-data phase relationship, other factors such as package flight time (package skew) and clock routing delays (internal to the device) affect the clock-to-data relationship at the sample point (in the IOB) and are difficult to characterize.

Xilinx recommends extensive investigation of the phase-shift setting during hardware integration and debugging. The phase-shift settings provided in the example design UCF are placeholders, and work successfully in back-annotated simulation of the example design.

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Xilinx UG144 manual Calculating DCM Phase-Shifting, Finding the Ideal Phase-Shift

UG144 specifications

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