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Xilinx UG144 manual Frame Reception with Errors, Receiving Inbound Frames

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Receiving Inbound Frames

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Frame Reception with Errors

Figure 5-2illustrates an unsuccessful frame reception (for example, a fragment frame or a frame with an incorrect FCS). In this case, the rx_bad_frame signal is asserted to the client at the end of the frame. It is then the responsibility of the client to drop the data already transferred for this frame.

The following conditions cause the assertion of rx_bad_frame:

•FCS errors occur.

•Packets are shorter than 64 bytes (undersize or fragment frames).

•Jumbo frames are received when jumbo frames are not enabled.

•VLAN frames of length 1519-1522 are received when VLAN frames are not enabled.

•A value of 0x0000 to 0x002D is in the type/length field. In this situation, the frame should be padded to minimum length. If it is not padded to exactly minimum frame length, the frame is marked as bad (when length/type checking is enabled).

•A value of 0x002E to 0x0600 is in the type/length field, but the real length of the received frame does not match this value (when length/type checking is enabled).

•Any control frame that is received is not exactly the minimum frame length (unless control frame length checks are disabled).

•gmii_rx_er is asserted at any point during frame reception.

•An error code is received in the 1-Gigabit frame extension field.

•A valid pause frame, addressed to the MAC, is received when flow control is enabled. Please see “Overview of Flow Control,” on page 53.

gmii_rx_clk

rx_data[7:0]

DA SA L/T DATA

rx_data_valid

rx_good_frame

rx_bad_frame

Figure 5-2:Frame Reception with Error

1-Gigabit Ethernet MAC v8.5 User Guide

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UG144 April 24, 2009

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Xilinx UG144 manual Frame Reception with Errors, Receiving Inbound Frames

Contents

UG144 April 24 LogiCORE IP Gigabit Ethernet MACGigabit Ethernet MAC v8.5 User Guide Date Version Revision Revision HistoryDIS Product Table of Contents Designing with the Core Configuration and Status Appendix C Calculating DCM Phase-Shifting Schedule of Figures 1Block Diagram2External Gmii Receiver Logic for Spartan-3, Spartan-3E, Figure A-2Frame Transfer across LocalLink Interface DIS Product Schedule of Tables Clocking and Resetting Interfacing to Other Cores About This Guide Guide ContentsTypographical ConventionsPreface About This Guide Convention Meaning or Use ExampleList of Acronyms Online DocumentConventions Acronym Spelled OutVhdl Preface About This Guide Acronym Spelled OutIntroduction Related Xilinx Ethernet Products and ServicesAbout the Core Recommended Design ExperienceTechnical Support SpecificationsFeedback Gemac CoreSystem Overview Core ArchitectureCore Components Core Interfaces Core InterfacesGmac Core with Optional Management Interface Core Architecture Core Interfaces Transmitter Interface Client Side InterfaceFlow Control Interface Receiver InterfaceMAC Unicast Address Optional Management Interface OptionalAsynchronous Reset Configuration Vector Optional7Reset Signal Direction Clock Domain Description Physical Side InterfaceMdio Interface Graphical User Interface Generating the CoreParameter Values in the XCO File Output Generation Generating the Core Designing with the Core Using the Example Design as a Starting PointGeneral Design Guidelines Design Steps11-Gigabit Ethernet MAC Core Example Design Designing with the CoreGeneral Design Guidelines Know the Degree of DifficultyImplementing the 1-Gigabit Ethernet MAC in Your Application Keep it Registered Recognize Timing Critical SignalsUse Supported Design Flows Make Only Allowed Modifications1Abbreviations Used in Timing Diagrams Definition Using the Client Side Data PathReceiving Inbound Frames Normal Frame ReceptionRxgoodframe, rxbadframe timing Using the Client Side Data PathReceiving Inbound Frames Frame Reception with ErrorsVlan Tagged Frames Client-Supplied FCS PassingEnabled Length/Type Field Error ChecksDisabled Maximum Permitted Frame Length5Receiver Statistics Vector Timing Receiver Statistics VectorDIS Product Length see Maximum Permitted Frame Normal Frame Transmission Transmitting Outbound FramesPadding Transmitting Outbound Frames7Frame Transmission with Client-supplied FCS Client Underrun9Transmission of a Vlan Tagged Frame Inter-Frame Gap AdjustmentTransmitter Statistics Vector 10Inter-Frame Gap AdjustmentName Bit 31 is equivalent to bit Flow Control Requirement Using Flow ControlOverview of Flow Control Flow Control Basics Using Flow ControlOverview of Flow Control Pause Control FramesTransmitting a Pause Control Frame Flow Control Operation of the GemacCore-initiated Pause Request Client Initiated Pause RequestCore Initiated Response to a Pause Request Receiving a Pause Control FrameClient Initiated Response to a Pause Request Flow Control Operation of the GemacMethod Flow Control Implementation Example4Flow Control Implementation Triggered from Fifo Occupancy Flow Control Implementation ExampleUsing Flow Control Gmii Transmitter Logic Using the Physical Side InterfaceImplementing External Gmii 1External Gmii Transmitter Logic Using the Physical Side InterfaceImplementing External Gmii Gmii Receiver LogicSpartan-3, Spartan-3E, Spartan-3A and Virtex-4 Devices DCM Reset circuitry 3External Gmii Receiver Logic for Virtex-5 Devices Virtex-5 DevicesRgmii Transmitter Logic Implementing External RgmiiImplementing External Rgmii Virtex-4 Devices5External Rgmii Transmitter Logic in Virtex-4 Devices 6External Rgmii Transmitter Logic in Virtex-5 Devices Rgmii Receiver Logic 7External Rgmii Receiver Logic Virtex-4 Devices 8External Rgmii Receiver Logic for Virtex-4 Devices 9External Rgmii Receiver Logic for Virtex-5 Devices 10RGMII Inband Status Decoding Logic Rgmii Inband Status Decoding LogicConnecting the Mdio to an External PHY Using the Mdio interfaceConnecting the Mdio to an Internally Integrated PHY Host Clock Frequency Configuration and StatusUsing the Optional Management Interface 2Configuration Registers Address Description Configuration RegistersConfiguration and Status Using the Optional Management Interface Receiver Configuration3Receiver Configuration Word Bit Default Description Receiver Configuration WordInterframe Gap Adjust Enable If ‘1,’ the transmitter will Transmitter Configuration6Flow Control Configuration Word Bit Default Description Flow Control ConfigurationAddress Filter Configuration Mdio Configuration10Address Table Configuration Word Bits Default Description Writing and Reading to and from the Configuration Registers11 Address Table Configuration Word 12Address Filter Mode Bits Default Description1Configuration Register Write Timing 3Address Table Write Timing Accessing the Address TableIntroduction to Mdio Mdio Interface5Typical MDIO-managed System Write TransactionRead Transaction Accessing Mdio With Gemac8MDIO Access through Management Interface Pause frame MAC Source Address470 Access without the Management InterfaceTransmitter Interframe Gap Adjust Enable Receive Flow Control Enable . When this bit Required Constraints Constraining the CoreConstraining the Core Period Constraints for Clock NetsRequired Constraints Timespecs for Critical Logic within the CoreGmii IOB Constraints Constraints when Implementing an External GmiiTimespecs for Reset Logic within the Core 1Input Gmii Timing Symbol Min Max Units Gmii Input Setup/Hold TimingVirtex-5 Devices Non-Virtex-5 devices Understanding Timing Reports for Gmii Setup/Hold TimingVirtex-5 devices with Delayed Data/Control Virtex-5 Devices with Delayed Clock Rgmii IOB Constraints Constraints when Implementing an External Rgmii2Input Rgmii Timing Symbol Min Typical Units Rgmii Input Setup/Hold TimingSpartan-3, Spartan-3E, Spartan-3A, and Virtex-4 Devices Rgmii DDR Constraints Understanding Timing Reports for Rgmii Setup/Hold timing 106 4Timing Report Setup/Hold Illustration 108 Clocking the Core Clocking and ResettingWith Internal Gmii With External GmiiMultiple Cores Clocking and ResettingWith Rgmii Standard Clocking Scheme3Clock Management Logic with External Gmii Multiple Cores Multiple Cores4Clock Management Logic with External Rgmii Multiple Cores Reset ConditionsEthernet 1000Base-X PCS/PMA or Sgmii Core Interfacing to Other CoresInterfacing to Other Cores Integration to Provide 1000BASE-X PCS with TBIEthernet 1000Base-X PCS/PMA or Sgmii Core 116 GTP Virtex-5 LXT and SXT DevicesClkdv Virtex-5 FXT DevicesEthernet Statistics Core Ethernet Statistics CoreIntegration to Provide Sgmii Functionality 120 Configuration Miim access Statistics Read 122 Implementing Your Design Using the Simulation ModelPre-implementation Simulation SynthesisXST-Verilog ImplementationGenerating the Xilinx Netlist Mapping the DesignPlacing-and-Routing the Design Post-Implementation SimulationStatic Timing Analysis Generating a BitstreamOther Implementation Information Using the ModelGMII/RGMII Using the Client-Side FifoTransmit Fifo Appendix a Using the Client-Side FifoInterfaces Interfaces Receive FifoData Flow Overview of LocalLink InterfaceFunctional Operation Functional OperationClock Requirements User Interface Data Width Conversion Expanding Maximum Frame SizeHardware Verification Core Verification, Compliance, and InteroperabilityVerification by Simulation 134 Finding the Ideal Phase-Shift Calculating DCM Phase-ShiftingDCM Phase-Shifting Appendix C Calculating DCM Phase-Shifting Receive Path Latency Core LatencyTransmit Path Latency Appendix D Core Latency