-- DISCONTINUED PRODUCT --

Required Constraints

R

The UCF syntax which follows targets the MDIO logic flip-flops and groups them together. Reduced clock period constraints are then applied.

############################################################

# MDIO Constraints: please do not edit#

############################################################

# Place the MDIO logic in it's own timing groups

 

INST "*gmac_core/BU2/U0/MANIFGEN?MANAGEN/PHY/ENABLE_REG"

TNM = "mdc_rising";

INST "*gmac_core/BU2/U0/MANIFGEN?MANAGEN/PHY/READY_INT"

TNM = "mdc_rising";

INST "*gmac_core/BU2/U0/MANIFGEN?MANAGEN/PHY/STATE_COUNT*"

TNM = FFS "mdc_rising";

INST "*gmac_core/BU2/U0/MANIFGEN?MANAGEN/PHY/MDIO_TRISTATE"

TNM = "mdc_falling";

INST "*gmac_core/BU2/U0/MANIFGEN?MANAGEN/PHY/MDIO_OUT"

TNM = "mdc_falling";

TIMEGRP "mdio_logic" = "mdc_rising" "mdc_falling";

 

TIMESPEC "TS_mdio1" = PERIOD "mdio_logic" 400 ns;

TIMESPEC "TS_mdio2" = FROM "mdc_rising" TO "mdc_falling" 200 ns;

Timespecs for Critical Logic within the Core

Signals must cross clock domains at certain points in the core, as described in the following sections.

Flow Control

Pause requests are received and decoding in the gmii_rx_clk domain and must be transferred into the gtx_clk domain to pause the transmitter. Therefore, whenever gmii_rx_clk and gtx_clk are derived from different clock sources, the following constraints must always be applied:

# Flow Control logic reclocking

INST "*gmac_core/BU2/U0/FLOW/RX_PAUSE/GOOD_FRAME_TO_TX" TNM="flow_rx_to_tx";

INST "*gmac_core/BU2/U0/FLOW/RX_PAUSE/PAUSE_REQ_TO_TX" TNM="flow_rx_to_tx"; INST "*gmac_core/BU2/U0/FLOW/RX_PAUSE_/AUSE_VALUE_TO_TX*" TNM="flow_rx_to_tx"; TIMESPEC "TS_flow_rx_to_tx" = FROM "flow_rx_to_tx" TO "tx_clock" 8000 ps;

Configuration

When the optional Management Interface is used with the core, configuration information is written synchronously to host_clk. Receiver configuration data must be transferred onto the gmii_rx_clk clock domain for use with the receiver and into the gtx_clk clock domain for use with the transmitter. The following UCF syntax targets this logic and a timing ignore attribute (TIG) is applied. It does not matter when configuration changes take place—the current configurations are sampled between frames by both the receiver and transmitter.

# Configuration Register reclocking

 

INST "*gmac_core/BU2/U0/MANIFGEN?MANAGEN/CONF/RX0_OUT*"

TNM="config_to_rx";

INST "*gmac_core/BU2/U0/MANIFGEN?MANAGEN/CONF/RX1_OUT*"

TNM="config_to_rx";

INST "*gmac_core/BU2/U0/MANIFGEN?MANAGEN/CONF/FC_OUT_29"

TNM="config_to_rx";

TIMESPEC "TS_config_to_rx" = FROM "config_to_rx" TO "rx_clock" TIG;

 

INST "*gmac_core/BU2/U0/MANIFGEN?MANAGEN/CONF/TX_OUT*"

TNM="config_to_tx";

INST "*gmac_core/BU2/U0/MANIFGEN?MANAGEN/CONF/FC_OUT_30"

TNM="config_to_tx";

TIMESPEC "TS_config_to_tx" = FROM "config_to_tx" TO "tx_clock" TIG;

 

1-Gigabit Ethernet MAC v8.5 User Guide

www.xilinx.com

95

UG144 April 24, 2009

Page 95
Image 95
Xilinx UG144 manual Timespecs for Critical Logic within the Core, Required Constraints

UG144 specifications

The Xilinx UG144, a comprehensive user guide for the versatile Zynq-7000 SoC (System on Chip) architecture, serves as an essential resource for developers and engineers designing embedded systems. Emphasizing the blend of programmable logic and processing power, this guide highlights the array of features and technologies that make the Zynq-7000 series particularly attractive for a wide range of applications.

One of the standout characteristics of the Zynq-7000 is its dual-core ARM Cortex-A9 processor, which delivers substantial performance for complex processing tasks. This soft processor enables high-speed computation, making it ideal for applications in fields such as automotive, industrial automation, and telecommunications. The guide emphasizes the ability to run multiple operating systems, including Linux and real-time operating systems, providing developers with versatile options for application design.

Additionally, the Xilinx UG144 outlines the extensive programmable logic resources integrated within the Zynq-7000 device. This FPGA fabric allows for customization and parallel processing capabilities, allowing designers to create powerful hardware accelerators tailored to specific application needs. The guide details how these programmable logic resources can easily interface with the ARM processors through a high-bandwidth AXI interface, promoting efficient data flow between the hardware and software components.

Key features highlighted in the UG144 include advanced connectivity options, including PCIe, USB, and Serial interfaces, which facilitate communication with other devices and systems. Furthermore, the guide provides insights into the supported design tools, such as the Xilinx Vivado Design Suite, which aids in both hardware and software co-design. This integrated environment significantly reduces development time while providing an efficient workflow for prototyping and testing.

In terms of performance optimizations, the guide discusses support for digital signal processing (DSP) capabilities, making the Zynq-7000 suitable for high-performance applications such as video processing and data analytics. The built-in DSP slices allow for efficient execution of complex mathematical functions, which is crucial for real-time data processing tasks.

Overall, the Xilinx UG144 guide encapsulates the versatility, performance, and flexibility of the Zynq-7000 SoC architecture. With its combination of ARM processing and programmable logic, along with robust connectivity options and development tools, it empowers engineers to create innovative solutions across a spectrum of industries, solidifying Xilinx's position as a leader in the field of embedded system design.