Xilinx UG144 manual 5External Rgmii Transmitter Logic in Virtex-4 Devices

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Chapter 7: Using the Physical Side Interface

						IOB LOGIC
IOB LOGIC			BUFGMUX		ODDR
	DCM CLK90
			rgmii_tx_clk_bufg
IBUFG			'1'	D1		OBUF
							rgmii_txc
gtx_clk	CLKIN		'0'	D2	Q		OPAD
IPAD
	FB	CLK0	gtx_clk_bufg	C
						IOB LOGIC
					ODDR
1-Gigabit Ethernet MAC Core
		gmii_txd[0]	gmii_txd_int[0]	D1		OBUF
		gmii_txd[4]	gmii_txd_int[4]	D2			rgmii_txd[0]
gtx_clk					Q
							OPAD
				C
						IOB LOGIC
					ODDR
		gmii_tx_en	gmii_tx_en_int	D1		OBUF
			gmii_tx_er_int	D2			rgmii_tx_ctl
		gmii_tx_er			Q		OPAD

C

Figure 7-5:External RGMII Transmitter Logic in Virtex-4 Devices

The logic required to forward the transmitter clock is also shown: this uses an ODDR register so that the clock signal produced incurs exactly on the same delay as the data and control signals. The rgmii_tx_clk clock signal is phase-shifted by 90 degrees in the DCM with respect to gtx_clk_bufg. This means that the rising edge of rgmii_txc occurs in the center of the data valid window—which maximizes setup and hold times across the interface, as specified in the RGMII v2.0 specification.

The use of the BUFGMUX shown, with one input connected to the DCM CLK90 output is included so that a reliable 125MHz clock source is always provided on global routing (when the DCM is held in reset, the DCM input clock is instead selected). This is required to always provided a reliable clock for the receiver logic DCM: see “DCM Reset circuitry”.

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		UG144 April 24, 2009