8MDIO Access through Management Interface

-- DISCONTINUED PRODUCT --

Using the Optional Management Interface

Figure 8-8shows access to the MDIO interface through the Management Interface.

host_clk
host_miim_sel
host_req
host_opcode1:0]
host_addr9:0]
host_wr_data15:0]	*
	*
host_rdy
host_rd_data[15:0]	*
	*

*If a read transaction is initiated, the host_rd_data bus is valid at the point indicated. If a write transaction is initiated, the host_wr_data bus must be valid at the indicated point. Simultaneous read and write is not permitted.

Figure 8-8:MDIO Access through Management Interface

For MDIO transactions, the following applies:

•host_miim_sel is ‘1’

•host_opcode[1:0] maps to the OP (opcode) field of the MDIO frame

•host_addr maps to the two address fields of the MDIO frame; PHYAD is host_addr[9:5], and REGAD is host_addr[4:0]

•host_wr_data[15:0] maps into the data field of the MDIO frame when performing a write operation

•The data field of the MDIO frame maps into host_rd_data[15:0] when performing a read operation

The GEMAC core signals the host that it is ready for an MDIO transaction by asserting host_miim_rdy. A read or write transaction on the MDIO is initiated by a pulse on the host_req signal. This pulse is ignored if the MDIO interface already has a transaction in progress. The GEMAC core then deasserts the host_miim_rdy signal while the transaction across the MDIO is in progress. When the transaction across the MDIO interface has been completed, the host_miim_rdy signal is asserted by the GEMAC core; if the transaction is a read, the data is available on the host_rd_data[15:0] bus at this time.

1-Gigabit Ethernet MAC v8.5 User Guide

www.xilinx.com

UG144 April 24, 2009

UG144 specifications

The Xilinx UG144, a comprehensive user guide for the versatile Zynq-7000 SoC (System on Chip) architecture, serves as an essential resource for developers and engineers designing embedded systems. Emphasizing the blend of programmable logic and processing power, this guide highlights the array of features and technologies that make the Zynq-7000 series particularly attractive for a wide range of applications.

One of the standout characteristics of the Zynq-7000 is its dual-core ARM Cortex-A9 processor, which delivers substantial performance for complex processing tasks. This soft processor enables high-speed computation, making it ideal for applications in fields such as automotive, industrial automation, and telecommunications. The guide emphasizes the ability to run multiple operating systems, including Linux and real-time operating systems, providing developers with versatile options for application design.

Additionally, the Xilinx UG144 outlines the extensive programmable logic resources integrated within the Zynq-7000 device. This FPGA fabric allows for customization and parallel processing capabilities, allowing designers to create powerful hardware accelerators tailored to specific application needs. The guide details how these programmable logic resources can easily interface with the ARM processors through a high-bandwidth AXI interface, promoting efficient data flow between the hardware and software components.

Key features highlighted in the UG144 include advanced connectivity options, including PCIe, USB, and Serial interfaces, which facilitate communication with other devices and systems. Furthermore, the guide provides insights into the supported design tools, such as the Xilinx Vivado Design Suite, which aids in both hardware and software co-design. This integrated environment significantly reduces development time while providing an efficient workflow for prototyping and testing.

In terms of performance optimizations, the guide discusses support for digital signal processing (DSP) capabilities, making the Zynq-7000 suitable for high-performance applications such as video processing and data analytics. The built-in DSP slices allow for efficient execution of complex mathematical functions, which is crucial for real-time data processing tasks.

Overall, the Xilinx UG144 guide encapsulates the versatility, performance, and flexibility of the Zynq-7000 SoC architecture. With its combination of ARM processing and programmable logic, along with robust connectivity options and development tools, it empowers engineers to create innovative solutions across a spectrum of industries, solidifying Xilinx's position as a leader in the field of embedded system design.

Xilinx UG144 manual 8MDIO Access through Management Interface

Models: UG144