-- DISCONTINUED PRODUCT --

Implementing External RGMII

RGMII Inband Status Decoding Logic

R

The inband status decoding logic is common to all device families. Figure 7-10illustrates the decoding of RGMII inband status information. This information is received through the RGMII interface between frames. The signal names and logic shown exactly match those delivered with the example design when the RGMII is selected.

1-Gigabit Ethernet MAC Core

gmii_rx_clk

gmii_rx_clk_bufg

 

gmii_rxd[0]

gmii_rxd_reg[0]

 

gmii_rxd[1]

gmii_rxd_reg[1]

gmii_rxd_reg[2]

gmii_rxd[2]

 

gmii_rxd[3]

gmii_rxd_reg[3]

 

gmii_rx_dv

gmii_rx_dv_reg

 

gmii_rx_er

gmii_rx_er_reg

 

 

 

OBUF

inband_link_status

D QOPAD

CE

OBUF

inband_clock_speed[0]

D QOPAD

CE

OBUF

inband_clock_speed[1]

D QOPAD

CE

OBUF

inband_duplex_status

D QOPAD

CE

RGMII RECEIVER LOGIC

Figure 7-10:RGMII Inband Status Decoding Logic

1-Gigabit Ethernet MAC v8.5 User Guide

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UG144 April 24, 2009

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Xilinx UG144 manual Rgmii Inband Status Decoding Logic, 10RGMII Inband Status Decoding Logic

UG144 specifications

The Xilinx UG144, a comprehensive user guide for the versatile Zynq-7000 SoC (System on Chip) architecture, serves as an essential resource for developers and engineers designing embedded systems. Emphasizing the blend of programmable logic and processing power, this guide highlights the array of features and technologies that make the Zynq-7000 series particularly attractive for a wide range of applications.

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