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Xilinx UG144 manual Constraints when Implementing an External Gmii, Gmii IOB Constraints

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Chapter 9: Constraining the Core

Timespecs for Reset Logic within the Core

Internally, the core is divided into clock/reset domains that group elements with common clock and reset signals. The reset circuitry for one of these domains is illustrated in Figure 10-5. This circuit provides controllable skews on the reset nets within the design. The following UCF syntax identifies the relevant reset logic and groups them together. Timing constraints are then applied to constrain the skews on the reset nets:

INST "*gmac_core/BU2/U0/SYNC_RX_RESET_I/RESET_OUT" TNM = "reset_dist_grp"; INST "*gmac_core/BU2/U0/SYNC_TX_RESET_I/RESET_OUT" TNM = "reset_dist_grp";

INST "*gmac_core/BU2/U0/G_SYNC_MGMT_RESET?SYNC_MGMT_RESET_HOST_I/RESET_OUT" TNM = "reset_dist_grp";

TIMESPEC "TS_reset_dist" = FROM "reset_dist_grp" 6100 ps;

Note: The third line in the preceding UCF syntax is only required when the optional Management Interface is used.

Constraints when Implementing an External GMII

The constraints defined in this section are implemented in the UCF for the example design delivered with the core. Sections from this UCF are copied into the following descriptions to provide examples. These examples should be studied in conjunction with the HDL source code for the example design and with the description “Implementing External GMII,” on page 61.

GMII IOB Constraints

The following constraints target the flip-flops that are inferred in the top-level HDL file for the example design; constraints are set to ensure that these are placed in IOBs.

#GMII Transmitter Constraints: place flip-flops in IOB

INST "*gmii_interface/gmii_txd_reg*" IOB = true; INST "*gmii_interface/gmii_tx_en_reg" IOB = true; INST "*gmii_interface/gmii_tx_er_reg" IOB = true;

#GMII Receiver Constraints: place flip-flops in IOB

INST "*gmii_interface/gmii_rxd_reg*" IOB = true; INST "*gmii_interface/gmii_rx_dv_reg" IOB = true; INST "*gmii_interface/gmii_rx_er_reg" IOB = true;

The GMII is a 3.3 volt signal-level interface which is not the default SelectIO™ standard. Therefore, use the following constraints with the device IO Banking rules.

INST "gmii_txd<?>"

IOSTANDARD = LVTTL;

INST "gmii_tx_en"

IOSTANDARD = LVTTL;

INST "gmii_tx_er"

IOSTANDARD = LVTTL;

INST "gmii_rxd<?>"

IOSTANDARD = LVTTL;

INST "gmii_rx_dv"

IOSTANDARD = LVTTL;

INST "gmii_rx_er"

IOSTANDARD = LVTTL;

INST "gmii_tx_clk"

IOSTANDARD = LVTTL;

INST "gmii_rx_clk"

IOSTANDARD = LVTTL;

In addition, the example design provides pad locking on the GMII for several families. This is a provided as a guideline only; there are no specific I/O location constraints for this core.

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1-Gigabit Ethernet MAC v8.5 User Guide

 

 

UG144 April 24, 2009

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Xilinx UG144 manual Constraints when Implementing an External Gmii, Timespecs for Reset Logic within the Core
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UG144 specifications

The Xilinx UG144, a comprehensive user guide for the versatile Zynq-7000 SoC (System on Chip) architecture, serves as an essential resource for developers and engineers designing embedded systems. Emphasizing the blend of programmable logic and processing power, this guide highlights the array of features and technologies that make the Zynq-7000 series particularly attractive for a wide range of applications.

One of the standout characteristics of the Zynq-7000 is its dual-core ARM Cortex-A9 processor, which delivers substantial performance for complex processing tasks. This soft processor enables high-speed computation, making it ideal for applications in fields such as automotive, industrial automation, and telecommunications. The guide emphasizes the ability to run multiple operating systems, including Linux and real-time operating systems, providing developers with versatile options for application design.

Additionally, the Xilinx UG144 outlines the extensive programmable logic resources integrated within the Zynq-7000 device. This FPGA fabric allows for customization and parallel processing capabilities, allowing designers to create powerful hardware accelerators tailored to specific application needs. The guide details how these programmable logic resources can easily interface with the ARM processors through a high-bandwidth AXI interface, promoting efficient data flow between the hardware and software components.

Key features highlighted in the UG144 include advanced connectivity options, including PCIe, USB, and Serial interfaces, which facilitate communication with other devices and systems. Furthermore, the guide provides insights into the supported design tools, such as the Xilinx Vivado Design Suite, which aids in both hardware and software co-design. This integrated environment significantly reduces development time while providing an efficient workflow for prototyping and testing.

In terms of performance optimizations, the guide discusses support for digital signal processing (DSP) capabilities, making the Zynq-7000 suitable for high-performance applications such as video processing and data analytics. The built-in DSP slices allow for efficient execution of complex mathematical functions, which is crucial for real-time data processing tasks.

Overall, the Xilinx UG144 guide encapsulates the versatility, performance, and flexibility of the Zynq-7000 SoC architecture. With its combination of ARM processing and programmable logic, along with robust connectivity options and development tools, it empowers engineers to create innovative solutions across a spectrum of industries, solidifying Xilinx's position as a leader in the field of embedded system design.