Xilinx UG144 manual Post-Implementation Simulation, Placing-and-Routing the Design

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Post-Implementation Simulation

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Placing-and-Routing the Design

Execute the par command to place-and-route your design logic components (mapped physical logic cells) contained within an NCD file in accordance with the layout and timing requirements specified within the PCF file. The par command outputs the placed and routed physical design to an NCD file.

An example of the par command is:

$ par top_level_module_name_map.ncd top_level_module_name.ncd \

top_level_module_name.pcf

Static Timing Analysis

Execute the trace command to evaluate timing closure on a design and create a Timing Report file (TWR) derived from static timing analysis of the Physical Design file (NCD). The analysis is typically based on constraints included in the optional PCF file.

An example of the trce command is:

$ trce -otop_level_module_name.twr top_level_module_name.ncd \

top_level_module_name.pcf

Generating a Bitstream

To create the configuration bitstream (BIT) file based on the contents of a physical implementation file (NCD), the bitgen command must be executed. The BIT file defines the behavior of the programmed FPGA. An example of the bitgen command is:

$ bitgen -wtop_level_module_name.ncd

Post-Implementation Simulation

The purpose of post-implementation simulation is to verify that the design as implemented in the FPGA works as expected.

Generating a Simulation Model

Run the netgen command to generate a chip-level simulation netlist for your design.

VHDL

$ netgen -sim -ofmt vhdl -ngm top_level_module_name_map.ngm \ -tm netlist top_level_module_name.ncd \ top_level_module_name_postimp.vhd

Verilog

$ netgen -sim -ofmt verilog -ngm top_level_module_name_map.ngm \ -tm netlist top_level_module_name.ncd \ top_level_module_name_postimp.v

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UG144 April 24, 2009