Expanding Maximum Frame Size

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Verilog

The compiler directive FULL_DUPLEX_ONLY is defined to allow for removal of logic and performance constraints that are necessary only in half-duplex operation, that is, when using with the Tri-Mode Ethernet MAC core. This directive can always be defined when the FIFO is used with the GEMAC.

The FIFO has two signal inputs specific to half-duplex operation, tx_collision and tx_retransmit. These signals are provided to make the FIFO compatible with both the 1-Gigabit Ethernet MAC and Tri-Mode Ethernet MAC cores, and should be tied to logic 0 when using the FIFO with the GEMAC core.

If the FIFO memory fills up, the dst_rdy_out_n signal is used to halt the LocalLink interface writing in data until space becomes available in the FIFO. If the FIFO memory fills up but no frames are available for transmission (for example, if a frame larger than 4000 bytes is written into the FIFO), the FIFO may assert the tx_overflow signal and continue to accept the rest of the frame from the user. The overflow frame will be dropped by the FIFO. This ensures that the LocalLink interface does not lock up. For this reason, it is recommended that the FIFO not be used with the GEMAC in jumbo frame mode for frames larger than 4000 bytes.

The transmit FIFO size is optimized to allow line rate transmission of maximum size

Ethernet frames at 1518 bytes in half-duplex operation.

When using the FIFO in full-duplex operation, the full block RAM capacity can be utilized at all times. As a whole frame must be stored in the FIFO block RAM before being presented to the MAC transmitter, the maximum size frame that can be handled is determined by the memory capacity of the FIFO (in this case 4000 bytes).

Both transmit and receive FIFO sizes can be expanded by the user to handle larger frame sizes. This can be done by instantiating further block RAMs into the FIFO design, expanding the block RAM address signals, and adding the necessary control signals. The HDL source files provide guidance in the comments on how to achieve this.

User Interface Data Width Conversion

Conversion of the user interface 8 bit data path to a 16, 32, 64 or 128 bit data path can be made by connecting the LocalLink interface directly to the Parameterizable LocalLink FIFO, Xilinx Application Note XAPP691, Parameterizable LocalLink FIFO found at direct.xilinx.com/bvdocs/appnotes/xapp691.pdf.

132	www.xilinx.com	1-Gigabit Ethernet MAC v8.5 User Guide
		UG144 April 24, 2009

UG144 specifications

The Xilinx UG144, a comprehensive user guide for the versatile Zynq-7000 SoC (System on Chip) architecture, serves as an essential resource for developers and engineers designing embedded systems. Emphasizing the blend of programmable logic and processing power, this guide highlights the array of features and technologies that make the Zynq-7000 series particularly attractive for a wide range of applications.

One of the standout characteristics of the Zynq-7000 is its dual-core ARM Cortex-A9 processor, which delivers substantial performance for complex processing tasks. This soft processor enables high-speed computation, making it ideal for applications in fields such as automotive, industrial automation, and telecommunications. The guide emphasizes the ability to run multiple operating systems, including Linux and real-time operating systems, providing developers with versatile options for application design.

Additionally, the Xilinx UG144 outlines the extensive programmable logic resources integrated within the Zynq-7000 device. This FPGA fabric allows for customization and parallel processing capabilities, allowing designers to create powerful hardware accelerators tailored to specific application needs. The guide details how these programmable logic resources can easily interface with the ARM processors through a high-bandwidth AXI interface, promoting efficient data flow between the hardware and software components.

Key features highlighted in the UG144 include advanced connectivity options, including PCIe, USB, and Serial interfaces, which facilitate communication with other devices and systems. Furthermore, the guide provides insights into the supported design tools, such as the Xilinx Vivado Design Suite, which aids in both hardware and software co-design. This integrated environment significantly reduces development time while providing an efficient workflow for prototyping and testing.

In terms of performance optimizations, the guide discusses support for digital signal processing (DSP) capabilities, making the Zynq-7000 suitable for high-performance applications such as video processing and data analytics. The built-in DSP slices allow for efficient execution of complex mathematical functions, which is crucial for real-time data processing tasks.

Overall, the Xilinx UG144 guide encapsulates the versatility, performance, and flexibility of the Zynq-7000 SoC architecture. With its combination of ARM processing and programmable logic, along with robust connectivity options and development tools, it empowers engineers to create innovative solutions across a spectrum of industries, solidifying Xilinx's position as a leader in the field of embedded system design.

Xilinx UG144 manual Expanding Maximum Frame Size, User Interface Data Width Conversion

Models: UG144

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Appendix A: Using the Client-Side FIFO

Verilog