Xilinx UG144 manual Constraining the Core, Required Constraints

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Chapter 9

Constraining the Core

This chapter defines the GEMAC core constraint requirements. An example UCF that implements the constraints defined in this chapter is provided with the HDL example design for the core.

See the 1-Gigabit Ethernet MAC Getting Started Guide for more information about the CORE Generator™ output files and detailed information about the HDL example design.

Required Constraints

Device, Package, and Speedgrade Selection

The GEMAC can be implemented in Virtex®-4, Virtex-5, Spartan®-3, Spartan-3E, and

Spartan-3A devices with the following attributes:

•Large enough to accommodate the core

•Contains a sufficient number of IOBs

•Operates at the following speed grades:

♦–4 for Spartan-3, Spartan-3E, and Spartan-3A devices

♦–10 for Virtex-4 FPGA

♦–1 for Virtex-5 FPGA

I/O Location Constraints

No specific I/O location constraints are required.

Placement Constraints

No specific placement constraints are required.

Timing Constraints

The core can have up to three separate clock domains: gtx_clk for the transmitter logic, gmii_rx_clk for the receiver logic, and host_clk for the optional management logic. These clock nets and the signals within the core that cross these clock domains must be constrained appropriately in a UCF.

The constraints defined in this section are implemented in the UCF for the example design delivered with the core. Sections from this UCF are copied into the following descriptions to provide examples. These examples should be studied in conjunction with the HDL source code for the example design.

1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com 93

UG144 April 24, 2009