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Chapter 3: Generating the Core

Component Name

The component name is used as the base name of the output files generated for the core. Names must begin with a letter and must be composed from the following characters: a through z, 0 through 9 and “_”.

Management Interface

Select this option to include the optional Management Interface (see “Using the Optional Management Interface,” on page 77). If this option is not selected, the core is generated with a replacement configuration vector (see “Access without the Management Interface,” on page 90). The default is to use the Management Interface.

Address Filter

Select this option to include the optional Address Filter. This prevents the reception of frames that are not addressed to this MAC (see “Address Filter,” on page 44). The default is to use the Address Filter.

Number of Address Table Entries

The Address Filter can be instantiated with an address table that holds up to 4 additional valid addresses. You may select an integer between 0 and 4 to define the number of addresses that are present in the table.

This option is only available when the Management Interface and Address Filter have been selected. The default is to use 4 address table entries.

Physical Interface

Depending on the target Xilinx FPGA architecture, it may be possible to select from two different physical interface choices for the core:

GMII. See Chapter 7, “Implementing External GMII”

RGMII. See Chapter 7, “Implementing External RGMII”

The choice of physical interface determines the content of the example design delivered with the core. The external GMII or RGMII is added in the HDL top-level design file. There is no change in the core netlist for this option. The default is the GMII physical interface.

Parameter Values in the XCO File

XCO file parameter names and their values are identical to the names and values shown in the GUI, except that underscore characters (_) are used instead of spaces. The text in an XCO file is not case-sensitive.

Table 3-1defines the XCO file parameters and values and summarizes the GUI defaults. The following is an example of the CSET parameters in an XCO file.

CSET component_name = abc123

CSET physical_interface = gmii

CSET management_interface = true

CSET address_filter = true

CSET no_of_address_table_entries = 4

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1-Gigabit Ethernet MAC v8.5 User Guide

 

 

UG144 April 24, 2009

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Xilinx UG144 manual Parameter Values in the XCO File

UG144 specifications

The Xilinx UG144, a comprehensive user guide for the versatile Zynq-7000 SoC (System on Chip) architecture, serves as an essential resource for developers and engineers designing embedded systems. Emphasizing the blend of programmable logic and processing power, this guide highlights the array of features and technologies that make the Zynq-7000 series particularly attractive for a wide range of applications.

One of the standout characteristics of the Zynq-7000 is its dual-core ARM Cortex-A9 processor, which delivers substantial performance for complex processing tasks. This soft processor enables high-speed computation, making it ideal for applications in fields such as automotive, industrial automation, and telecommunications. The guide emphasizes the ability to run multiple operating systems, including Linux and real-time operating systems, providing developers with versatile options for application design.

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Key features highlighted in the UG144 include advanced connectivity options, including PCIe, USB, and Serial interfaces, which facilitate communication with other devices and systems. Furthermore, the guide provides insights into the supported design tools, such as the Xilinx Vivado Design Suite, which aids in both hardware and software co-design. This integrated environment significantly reduces development time while providing an efficient workflow for prototyping and testing.

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