Xilinx UG144 manual Accessing the Address Table, 3Address Table Write Timing

-- DISCONTINUED PRODUCT --

Using the Optional Management Interface

R

Accessing the Address Table

To write to a specific entry in the address table, you must first write the least significant 32- bits of the address into the Address Table Configuration (Word 0) register. You then write the most significant 16 bits together with the location in the table (bits 17–16) to the Address Table Configuration (Word1) register with bit 23 (read not write) set to ‘0.’ This is shown in Figure 8-3. Although it is shown in the figure, there is no requirement for the two writes to be on adjacent cycles.

hostclk
hostmiimsel
hostopcode[1]
hostaddr[8:0]	0x188	0x18C
hostaddr[9]

hostwrdata[31:0]

ADDR[31:0]

BIT31 BIT0

BITS15..0 = ADDR[47:32]

BITS17..16 = LOCATION

BIT23 = 0

Figure 8-3:Address Table Write Timing

As shown in Figure 8-4, you must write to the Address Table Configuration register (Word

1)with the location set to the desired table entry and bit 23 set to ‘1’ to read from the address table. On the next cycle the least significant word appears on the hostrddata bus. One cycle afterwards, the most significant 16-bits are output on the lower 16 bits of the bus.

1-Gigabit Ethernet MAC v8.5 User Guide www.xilinx.com 85

UG144 April 24, 2009