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Xilinx UG144 manual Accessing the Address Table, 3Address Table Write Timing

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Using the Optional Management Interface

R

Accessing the Address Table

To write to a specific entry in the address table, you must first write the least significant 32- bits of the address into the Address Table Configuration (Word 0) register. You then write the most significant 16 bits together with the location in the table (bits 17–16) to the Address Table Configuration (Word1) register with bit 23 (read not write) set to ‘0.’ This is shown in Figure 8-3. Although it is shown in the figure, there is no requirement for the two writes to be on adjacent cycles.

hostclk
hostmiimsel
hostopcode[1]
hostaddr[8:0]	0x188	0x18C
hostaddr[8:0]
hostaddr[9]

hostwrdata[31:0]

ADDR[31:0]

BIT31					BIT0

BITS15..0 = ADDR[47:32]

BITS17..16 = LOCATION

BIT23 = 0

Figure 8-3:Address Table Write Timing

As shown in Figure 8-4, you must write to the Address Table Configuration register (Word

1)with the location set to the desired table entry and bit 23 set to ‘1’ to read from the address table. On the next cycle the least significant word appears on the hostrddata bus. One cycle afterwards, the most significant 16-bits are output on the lower 16 bits of the bus.

1-Gigabit Ethernet MAC v8.5 User Guide

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UG144 April 24, 2009

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Xilinx UG144 manual Accessing the Address Table, 3Address Table Write Timing

Contents

UG144 April 24 LogiCORE IP Gigabit Ethernet MACGigabit Ethernet MAC v8.5 User Guide Date Version Revision Revision HistoryDIS Product Table of Contents Designing with the Core Configuration and Status Appendix C Calculating DCM Phase-Shifting Schedule of Figures 1Block Diagram2External Gmii Receiver Logic for Spartan-3, Spartan-3E, Figure A-2Frame Transfer across LocalLink Interface DIS Product Schedule of Tables Clocking and Resetting Interfacing to Other Cores About This Guide Guide ContentsTypographical ConventionsPreface About This Guide Convention Meaning or Use ExampleList of Acronyms Online DocumentConventions Acronym Spelled OutVhdl Preface About This Guide Acronym Spelled OutIntroduction Related Xilinx Ethernet Products and ServicesAbout the Core Recommended Design ExperienceTechnical Support SpecificationsFeedback Gemac CoreSystem Overview Core ArchitectureCore Components Gmac Core with Optional Management Interface Core InterfacesCore Interfaces Core Architecture Core Interfaces Transmitter Interface Client Side InterfaceFlow Control Interface Receiver InterfaceMAC Unicast Address Optional Management Interface OptionalAsynchronous Reset Configuration Vector Optional7Reset Signal Direction Clock Domain Description Physical Side InterfaceMdio Interface Graphical User Interface Generating the CoreParameter Values in the XCO File Output Generation Generating the Core Designing with the Core Using the Example Design as a Starting PointGeneral Design Guidelines Design Steps11-Gigabit Ethernet MAC Core Example Design Designing with the CoreImplementing the 1-Gigabit Ethernet MAC in Your Application Know the Degree of DifficultyGeneral Design Guidelines Keep it Registered Recognize Timing Critical SignalsUse Supported Design Flows Make Only Allowed Modifications1Abbreviations Used in Timing Diagrams Definition Using the Client Side Data PathReceiving Inbound Frames Normal Frame ReceptionRxgoodframe, rxbadframe timing Using the Client Side Data PathReceiving Inbound Frames Frame Reception with ErrorsVlan Tagged Frames Client-Supplied FCS PassingEnabled Length/Type Field Error ChecksDisabled Maximum Permitted Frame Length5Receiver Statistics Vector Timing Receiver Statistics VectorDIS Product Length see Maximum Permitted Frame Normal Frame Transmission Transmitting Outbound FramesPadding Transmitting Outbound Frames7Frame Transmission with Client-supplied FCS Client Underrun9Transmission of a Vlan Tagged Frame Inter-Frame Gap AdjustmentTransmitter Statistics Vector 10Inter-Frame Gap AdjustmentName Bit 31 is equivalent to bit Overview of Flow Control Using Flow ControlFlow Control Requirement Flow Control Basics Using Flow ControlOverview of Flow Control Pause Control FramesTransmitting a Pause Control Frame Flow Control Operation of the GemacCore-initiated Pause Request Client Initiated Pause RequestCore Initiated Response to a Pause Request Receiving a Pause Control FrameClient Initiated Response to a Pause Request Flow Control Operation of the GemacMethod Flow Control Implementation Example4Flow Control Implementation Triggered from Fifo Occupancy Flow Control Implementation ExampleUsing Flow Control Implementing External Gmii Using the Physical Side InterfaceGmii Transmitter Logic 1External Gmii Transmitter Logic Using the Physical Side InterfaceSpartan-3, Spartan-3E, Spartan-3A and Virtex-4 Devices Gmii Receiver LogicImplementing External Gmii DCM Reset circuitry 3External Gmii Receiver Logic for Virtex-5 Devices Virtex-5 DevicesRgmii Transmitter Logic Implementing External RgmiiImplementing External Rgmii Virtex-4 Devices5External Rgmii Transmitter Logic in Virtex-4 Devices 6External Rgmii Transmitter Logic in Virtex-5 Devices Rgmii Receiver Logic 7External Rgmii Receiver Logic Virtex-4 Devices 8External Rgmii Receiver Logic for Virtex-4 Devices 9External Rgmii Receiver Logic for Virtex-5 Devices 10RGMII Inband Status Decoding Logic Rgmii Inband Status Decoding LogicConnecting the Mdio to an Internally Integrated PHY Using the Mdio interfaceConnecting the Mdio to an External PHY Using the Optional Management Interface Configuration and StatusHost Clock Frequency Configuration and Status Configuration Registers2Configuration Registers Address Description Using the Optional Management Interface Receiver Configuration3Receiver Configuration Word Bit Default Description Receiver Configuration WordInterframe Gap Adjust Enable If ‘1,’ the transmitter will Transmitter Configuration6Flow Control Configuration Word Bit Default Description Flow Control ConfigurationAddress Filter Configuration Mdio Configuration10Address Table Configuration Word Bits Default Description Writing and Reading to and from the Configuration Registers11 Address Table Configuration Word 12Address Filter Mode Bits Default Description1Configuration Register Write Timing 3Address Table Write Timing Accessing the Address TableIntroduction to Mdio Mdio Interface5Typical MDIO-managed System Write TransactionRead Transaction Accessing Mdio With Gemac8MDIO Access through Management Interface Pause frame MAC Source Address470 Access without the Management InterfaceTransmitter Interframe Gap Adjust Enable Receive Flow Control Enable . When this bit Required Constraints Constraining the CoreConstraining the Core Period Constraints for Clock NetsRequired Constraints Timespecs for Critical Logic within the CoreTimespecs for Reset Logic within the Core Constraints when Implementing an External GmiiGmii IOB Constraints 1Input Gmii Timing Symbol Min Max Units Gmii Input Setup/Hold TimingVirtex-5 Devices Virtex-5 devices with Delayed Data/Control Understanding Timing Reports for Gmii Setup/Hold TimingNon-Virtex-5 devices Virtex-5 Devices with Delayed Clock Rgmii IOB Constraints Constraints when Implementing an External Rgmii2Input Rgmii Timing Symbol Min Typical Units Rgmii Input Setup/Hold TimingSpartan-3, Spartan-3E, Spartan-3A, and Virtex-4 Devices Rgmii DDR Constraints Understanding Timing Reports for Rgmii Setup/Hold timing 106 4Timing Report Setup/Hold Illustration 108 Clocking the Core Clocking and ResettingWith Internal Gmii With External GmiiMultiple Cores Clocking and ResettingWith Rgmii Standard Clocking Scheme3Clock Management Logic with External Gmii Multiple Cores Multiple Cores4Clock Management Logic with External Rgmii Multiple Cores Reset ConditionsEthernet 1000Base-X PCS/PMA or Sgmii Core Interfacing to Other CoresInterfacing to Other Cores Integration to Provide 1000BASE-X PCS with TBIEthernet 1000Base-X PCS/PMA or Sgmii Core 116 GTP Virtex-5 LXT and SXT DevicesClkdv Virtex-5 FXT DevicesIntegration to Provide Sgmii Functionality Ethernet Statistics CoreEthernet Statistics Core 120 Configuration Miim access Statistics Read 122 Implementing Your Design Using the Simulation ModelPre-implementation Simulation SynthesisXST-Verilog ImplementationGenerating the Xilinx Netlist Mapping the DesignPlacing-and-Routing the Design Post-Implementation SimulationStatic Timing Analysis Generating a BitstreamOther Implementation Information Using the ModelGMII/RGMII Using the Client-Side FifoInterfaces Appendix a Using the Client-Side FifoTransmit Fifo Interfaces Receive FifoData Flow Overview of LocalLink InterfaceClock Requirements Functional OperationFunctional Operation User Interface Data Width Conversion Expanding Maximum Frame SizeVerification by Simulation Core Verification, Compliance, and InteroperabilityHardware Verification 134 DCM Phase-Shifting Calculating DCM Phase-ShiftingFinding the Ideal Phase-Shift Appendix C Calculating DCM Phase-Shifting Transmit Path Latency Core LatencyReceive Path Latency Appendix D Core Latency