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Chapter 9: Constraining the Core

Data Sheet report:

-----------------

All values displayed in nanoseconds (ns)

Setup/Hold to		clock rgmii_rxc
------------	+	------------+	------------+------------------	+	--------	+
		Setup to	Hold to	Clock
Source		clk (edge) clk (edge) Internal Clock(s) Phase
------------	+	------------+	------------+------------------	+	--------	+
rgmii_rx_ctl		0.810(R)	0.933(R) rgmii_rx_clk_bufg		0.000
		-3.214(F)	4.959(F) rgmii_rx_clk_bufg		4.000
rgmii_rxd<0>		0.811(R)	0.940(R) rgmii_rx_clk_bufg		0.000
		-3.213(F)	4.966(F) rgmii_rx_clk_bufg		4.000
rgmii_rxd<1>		0.801(R)	0.946(R) rgmii_rx_clk_bufg		0.000
		-3.223(F)	4.972(F) rgmii_rx_clk_bufg		4.000
rgmii_rxd<2>		0.818(R)	0.929(R) rgmii_rx_clk_bufg		0.000
		-3.206(F)	4.955(F) rgmii_rx_clk_bufg		4.000
rgmii_rxd<3>		0.809(R)	0.936(R) rgmii_rx_clk_bufg		0.000
		-3.215(F)	4.962(F) rgmii_rx_clk_bufg		4.000
------------	+	------------+	------------+------------------	+	--------	+

Virtex-5 Devices with Delayed Clock

Setup and Hold results for the RGMII input bus can be found in the data sheet section of the Timing Report. However, depending on how the setup/hold requirements have been met, it may not be immediately obvious how the results relate to Figure 9-3. Following is an example for the RGMII report from a Virtex-5 device where the clock has been delayed to meet the setup/hold requirements.

Data Sheet report:

-----------------

All values displayed in nanoseconds (ns)

Setup/Hold to		clock rgmii_rxc
------------	+	------------+	------------+------------------	+	--------	+
		Setup to	Hold to	Clock
Source		clk (edge) clk (edge) Internal Clock(s) Phase
------------	+	------------+	------------+------------------	+	--------	+
rgmii_rx_ctl		-7.178(R)	8.880(R) rgmii_rx_clk_bufg		0.000
		-11.178(F)	12.880(F) rgmii_rx_clk_bufg		4.000
rgmii_rxd<0>		-7.192(R)	8.893(R) rgmii_rx_clk_bufg		0.000
		-11.192(F)	12.893(F) rgmii_rx_clk_bufg		4.000
rgmii_rxd<1>		-7.182(R)	8.884(R) rgmii_rx_clk_bufg		0.000
		-11.182(F)	12.884(F) rgmii_rx_clk_bufg		4.000
rgmii_rxd<2>		-7.180(R)	8.882(R) rgmii_rx_clk_bufg		0.000
		-11.180(F)	12.882(F) rgmii_rx_clk_bufg		4.000
rgmii_rxd<3>		-7.179(R)	8.881(R) rgmii_rx_clk_bufg		0.000
		-11.179(F)	12.881(F) rgmii_rx_clk_bufg		4.000
------------	+	------------+	------------+------------------	+	--------	+

Each Input lists two sets of values—one corresponding to the +ve edge of the clock and one to the –ve edge. The first set listed corresponds to +ve edge, which occurs at time 8 ns as we have delayed the clock to use the following +ve edge.

The implementation requires –7.179 ns of setup to the +ve edge. Figure 9-4illustrates that this represents 0.821 ns relative to the following rising edge of the clock (since the IDELAY has acted to delay the clock by an entire period when measured from the input flip-flop).

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		UG144 April 24, 2009

UG144 specifications

The Xilinx UG144, a comprehensive user guide for the versatile Zynq-7000 SoC (System on Chip) architecture, serves as an essential resource for developers and engineers designing embedded systems. Emphasizing the blend of programmable logic and processing power, this guide highlights the array of features and technologies that make the Zynq-7000 series particularly attractive for a wide range of applications.

One of the standout characteristics of the Zynq-7000 is its dual-core ARM Cortex-A9 processor, which delivers substantial performance for complex processing tasks. This soft processor enables high-speed computation, making it ideal for applications in fields such as automotive, industrial automation, and telecommunications. The guide emphasizes the ability to run multiple operating systems, including Linux and real-time operating systems, providing developers with versatile options for application design.

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Key features highlighted in the UG144 include advanced connectivity options, including PCIe, USB, and Serial interfaces, which facilitate communication with other devices and systems. Furthermore, the guide provides insights into the supported design tools, such as the Xilinx Vivado Design Suite, which aids in both hardware and software co-design. This integrated environment significantly reduces development time while providing an efficient workflow for prototyping and testing.

In terms of performance optimizations, the guide discusses support for digital signal processing (DSP) capabilities, making the Zynq-7000 suitable for high-performance applications such as video processing and data analytics. The built-in DSP slices allow for efficient execution of complex mathematical functions, which is crucial for real-time data processing tasks.

Overall, the Xilinx UG144 guide encapsulates the versatility, performance, and flexibility of the Zynq-7000 SoC architecture. With its combination of ARM processing and programmable logic, along with robust connectivity options and development tools, it empowers engineers to create innovative solutions across a spectrum of industries, solidifying Xilinx's position as a leader in the field of embedded system design.

Xilinx UG144 manual 106

Models: UG144

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Chapter 9: Constraining the Core

Virtex-5 Devices with Delayed Clock

1-Gigabit Ethernet MAC v8.5 User Guide

UG144 specifications