-- DISCONTINUED PRODUCT --

Ethernet Statistics Core

R

Features of this configuration include:

Direct internal connections are made between the GMII interfaces between the two cores.

If the GEMAC has been generated with the optional Management Interface, the MDIO port can be connected up to that of the Ethernet 1000BASE-X PCS/PMA or SGMII core to access its embedded configuration and status registers. See “Using the Optional Management Interface.”

Due to the embedded Receiver Elastic Buffer in the Ethernet 1000BASE-X PCS/PMA or SGMII core, the entire GMII is synchronous to a single clock domain. For this reason, userclk2 is used as the 125 MHz reference clock for both cores and the transmitter and receiver logic of the GEMAC core now operate in the same clock domain. This allows clock crossing constraints between the gtx_clk and gmii_rx_clk clock domains to be removed from the GEMAC UCF. See “Timespecs for Critical Logic within the Core.”

Integration to Provide SGMII Functionality

The connections between the two cores to provide SGMII functionality are identical to the connections required for 1000BASE-X PCS and PMA using the device-specific RocketIO transceiver. The only difference is that the Ethernet 1000BASE-X PCS/PMA or SGMII core is generated with the SGMII option. See “Integration to Provide 1000BASE-X PCS and PMA using a RocketIO Transceiver” for a description of SGMII integration.

Ethernet Statistics Core

The Ethernet Statistics core can be integrated in a single device with the 1-Gigabit Ethernet MAC core. Using the Ethernet Statistics core lets you

Count statistics based on the rx_statistics_vector and tx_statistics_vector outputs from the MAC

Select 32-bit or 64-bit counters

Specify which statistics are counted and have precise control of the conditions under which the counters are incremented

Read statistics optionally through the host interface of the GEMAC or independently of the MAC

A description of the latest available IP Update containing the Ethernet Statistics core and instructions on obtaining the IP update can be found on the Ethernet Statistics product page.

Connecting the Ethernet Statistics Core to Provide Statistics Gathering

The Ethernet Statistics core interfaces directly to the 1-Gigabit Ethernet MAC core. The Ethernet Statistics core takes in the tx_statistics_vector and rx_statistics_vector as inputs. Statistics values gathered can then be read out through the Statistics core Management Interface, that can be shared with the MAC Management Interface.

1-Gigabit Ethernet MAC v8.5 User Guide

www.xilinx.com

119

UG144 April 24, 2009

Page 119
Image 119
Xilinx UG144 manual Ethernet Statistics Core, Integration to Provide Sgmii Functionality

UG144 specifications

The Xilinx UG144, a comprehensive user guide for the versatile Zynq-7000 SoC (System on Chip) architecture, serves as an essential resource for developers and engineers designing embedded systems. Emphasizing the blend of programmable logic and processing power, this guide highlights the array of features and technologies that make the Zynq-7000 series particularly attractive for a wide range of applications.

One of the standout characteristics of the Zynq-7000 is its dual-core ARM Cortex-A9 processor, which delivers substantial performance for complex processing tasks. This soft processor enables high-speed computation, making it ideal for applications in fields such as automotive, industrial automation, and telecommunications. The guide emphasizes the ability to run multiple operating systems, including Linux and real-time operating systems, providing developers with versatile options for application design.

Additionally, the Xilinx UG144 outlines the extensive programmable logic resources integrated within the Zynq-7000 device. This FPGA fabric allows for customization and parallel processing capabilities, allowing designers to create powerful hardware accelerators tailored to specific application needs. The guide details how these programmable logic resources can easily interface with the ARM processors through a high-bandwidth AXI interface, promoting efficient data flow between the hardware and software components.

Key features highlighted in the UG144 include advanced connectivity options, including PCIe, USB, and Serial interfaces, which facilitate communication with other devices and systems. Furthermore, the guide provides insights into the supported design tools, such as the Xilinx Vivado Design Suite, which aids in both hardware and software co-design. This integrated environment significantly reduces development time while providing an efficient workflow for prototyping and testing.

In terms of performance optimizations, the guide discusses support for digital signal processing (DSP) capabilities, making the Zynq-7000 suitable for high-performance applications such as video processing and data analytics. The built-in DSP slices allow for efficient execution of complex mathematical functions, which is crucial for real-time data processing tasks.

Overall, the Xilinx UG144 guide encapsulates the versatility, performance, and flexibility of the Zynq-7000 SoC architecture. With its combination of ARM processing and programmable logic, along with robust connectivity options and development tools, it empowers engineers to create innovative solutions across a spectrum of industries, solidifying Xilinx's position as a leader in the field of embedded system design.