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AHB SRAM/NOR, PL241 manual
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Contents
Main
PrimeCell AHB SRAM/NOR Memory Controller (PL241)
Technical Reference Manual Copyright 2006 ARM Limited. All rights reserved.
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List of Tables PrimeCell AHB SRAM/NOR Memory Controller (PL241) Technical Reference Manual
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List of Figures PrimeCell AHB SRAM/NOR Memory Controller (PL241) Technical Reference Manual
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About this manual
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Feedback
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1.1 About the AHB MC
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1.2 Supported devices
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2.1 Functional description
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2.2 SMC
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2.3 Functional operation
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2.4 SMC functional operation
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Figure 2-12 Device pin mechanism
Figure 2-13 Software mechanism
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Table2-4 and Table 2-5 list the smc_opmode0_<0-3> and SRAM Register settings.
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Table2-8 and Table 2-9 list the smc_opmode0_<0-3> and SRAM Register settings.
Table2-10 and Table 2-11 list the smc_opmode0_<0-3> and SRAM Register settings.
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Table2-14 and Table 2-15 list the smc_opmode0_<0-3> and SRAM Register settings.
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Table2-18 and Table 2-19 list the smc_opmode0_<0-3> and SRAM Register settings.
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3.1 About the programmers model
3.2 Register summary
Figure 3-2 shows the SMC configuration register map.
0-3
Figure 3-3 shows the SMC chip<
Figure 3-2 SMC configuration register map
Figure 3-5 shows the SMC peripheral and PrimeCell configuration register map.
Table3-1 lists th e SMC Registers.
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3.3 Register descriptions
Table3-3 lists the register bit assignments.
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Table3-8 lists the register bit assignments.
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Table3-11 lists the register bit assignments.
Table3-12 lists the register bit assignments.
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. The register can be accessed with one wait state. Table3-19 lists the register bit assignments.
Figure 3-19 shows the register bit assignments.
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4.1 SMC integration test registers
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5.1 Memory initialization
Figure 5-1 SMC and memory initialization sheet 1 of 3
Figure 5-2 SMC and memory initialization sheet 2 of 3
Figure 5-3 SMC and memory initialization sheet 3 of 3
Where: x = denotes the appropriate chip select.
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A.1 About the signals list
This appendix lists the PL241 signals. Figure A-1 shows how the signals are grouped.
Figure A-1 AHB MC PL241 grouping of signals
where: AHBC = AHB Configuration signals
A.2 Clocks and resets
TableA-1 lists the clock and reset signals.
A.3 AHB signals
A.4 SMC memory interface signals
TableA-3 lists the SMC memory inter face signals.
A.5 SMC miscellaneous signals
TableA-4 lists the SMC miscellaneous signals.
A.6 Low-power interface
TableA-5 lists the low-power interface signals.
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A.8 Scan chains
TableA-7 lists the scan chain signals.
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Glossary