
Functional Overview
2.2.6Pad interface
The pad interface module provides a registered I/O interface for data and control signals. It also contains interrupt generation logic.
Figure 2-4 shows the SRAM pad interface external signals. Clock and reset signals are omitted.
VPFBGDWDBLQB>@
VPFBIEFONBLQB
65$0
SDGLQWHUIDFH
VPFBLQWB
VPFBZDLWB
VPFBDGYBQB VPFBEDDBQB
VPFBEOVBQB>@
VPFBFONBRXWB>@
VPFBFUHB VPFBFVBQB>@
VPFBGDWDBHQB VPFBGDWDBRXWB>@
VPFBRHBQB VPFBZHBQB
Figure 2-4 SMC SRAM pad interface external connections
2.2.7Interrupts
The SRAM memory interface support interrupts. The interrupt is triggered on the rising edge of the smc_int_0 input for the SRAM memory interface.
See Interrupts operation on page
Copyright © 2006 ARM Limited. All rights reserved. | ARM DDI 0389B |