Chapter Programmer’s Model for Test | SMC Networks PL241 guide

Contents

Chapter 4	Programmer’s Model for Test
	4.1	SMC integration test registers	4-2
Chapter 5	Device Driver Requirements
	5.1	Memory initialization	5-2
Appendix A	Signal Descriptions
	A.1	About the signals list	A-2
	A.2	Clocks and resets	A-3
	A.3	AHB signals	A-4
	A.4	SMC memory interface signals	A-5
	A.5	SMC miscellaneous signals	A-6
	A.6	Low-power interface	A-7
	A.7	Configuration signal	A-8
	A.8	Scan chains	A-9

Glossary

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Copyright © 2006 ARM Limited. All rights reserved.

ARM DDI 0389B

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SMC Networks PL241, AHB SRAM/NOR manual Chapter Programmer’s Model for Test

Contents

PrimeCell AHB SRAM/NOR Memory Controller PL241 Technical Reference Manual PrimeCell AHB SRAM/NOR Memory Controller PL241Copyright 2006 ARM Limited. All rights reserved Contents Chapter Programmer’s Model for Test List of Tables List of Tables List of Figures Figure A-1 AHB MC PL241 grouping of signals Preface Feedback on Using this manual About this manualProduct revision status Intended audience Typographical ConventionsBold Timing diagrams Signals Further reading NumberingARM publications Feedback on this product FeedbackFeedback on this manual Introduction This section describes About the AHB MCSMC on AHB interface AHB to APB bridge 3 SMC Low-power interfacesClock domains Supported devices Intel W18 series NOR FLASH, for example 28f128W18td Introduction Copyright 2006 ARM Limited. All rights reserved Functional Overview Functional description This section is divided into Smcmreset0n Low-power interfaceAHB clock domain Static memory clock domain SMC Main blocks of the SMC areFormat on Interrupts on SMC interface APB slave interfaceFormat Memory manager Pad interface Interrupts AHB interface operation Functional operationAHB fixed burst types Undefined length Incr bursts Bufferable bit of the Hprot signalBroken bursts Read after write hazard detection buffer AHB response signalsLocked transfers Big-endian 32-bit mode Removal of AHB error response logicRegistered Hwdata AHB to APB bridge operation Clock domain operation Ahbc memory map Low-power interface operation Static memory clocking options1lists the static memory clocking options Static memory clocking options Where Domain is ahb or smc An active output Domaincactive Accepting requests Operating states SMC functional operationSMC states are as follows Clocking and resets Clocking Resets Miscellaneous signals Smcuserconfig70Smcuserstatus70 Smcagtm0sync Format block APB slave interface operationHazard handling Sram memory accesses Memory burst length Chip configuration registers Low-power operationMemory manager operation 11 Chip configuration registers Device pin mechanism Direct commandsSoftware mechanism 12 Device pin mechanism 13 Software mechanism Interrupts operation Sram timing tables and diagramsMemory interface operation Asynchronous read opmode chip register settings Asynchronous read Sram cycles register settings 4and -5list the smcopmode00-3 and Sram Register settings 14 Asynchronous read Asynchronous write opmode chip register settings 6and -7list the smcopmode00-3 and Sram Register settingsAsynchronous write Sram cycles register settings 10and -11list the smcopmode00-3 and Sram Register settings 8and -9list the smcopmode00-3 and Sram Register settings10 Page read opmode chip register settings 12 Synchronous burst read opmode chip register settings 12and -13list the smcopmode00-3 and Sram Register settings13 Synchronous burst read Sram cycles register settings 19 Synchronous burst read 14and -15list the smcopmode00-3 and Sram Register settings 20 Synchronous burst read in multiplexed-mode 16 Synchronous burst write opmode chip register settings 16and -17list the smcopmode00-3 and Sram Register settings17 Synchronous burst write Sram cycles register settings 18and -19list the smcopmode00-3 and Sram Register settings 22 Synchronous burst write in multiplexed-mode 20and -21list the smcopmode00-3 and Sram Register settings B0100 B0110 B001 TCEOE is only required if wait is asserted when oen goes LOW TWC = ARM DDI 0389B Programmer’s Model About the programmer’s model 2shows the SMC configuration register map Register summary Name Base offset Type Reset value Description 1lists the SMC Registers Register summary Register descriptions This section describes the SMC registersSMC Memory Controller Status Register at 2lists the register bit assignments 3lists the register bit assignments SMC Memory Interface Configuration Register atBits Name Function SMC Set Configuration Register at Smcmemccfgset Register bit assignments SMC Clear Configuration Register at 0x100C 4lists the register bit assignments5lists the register bit assignments Smcmemccfgclr Register bit assignments Bits Name Function 6lists the register bit assignments SMC Direct Command Register atSmcdirectcmd Register bit assignments SMC Set Cycles Register at Lists the register bit assignments SMC Set Opmode Register at 12 smcsetopmode Register bit assignments 8lists the register bit assignments Smcsetopmode Register bit assignments Memory width mw field SMC Sram Cycles Registers 0-3 at 0x1100, 0x1120, 0x1140 SMC Refresh Period 0 Register atSmcrefreshperiod0 Register bit assignments 10lists the register bit assignments SMC Opmode Registers 0-3 at 0x1104, 0x1124, 0x1144 11lists the register bit assignments SMC User Status Register at 12lists the register bit assignments11 smcopmode Register bit assignments 12 smcuserstatus Register bit assignments SMC User Configuration Register at 13 smcuserconfig Register bit assignments13 lists the register bit assignments Bits Name Description SMC Peripheral Identification Register Following section describe the smcperiphid Registers15 smcperiphid0 Register bit assignments Bits Name Function 16 smcperiphid1 Register bit assignments Bits Name Function 17 smcperiphid2 Register bit assignments Bits Name Function SMC PrimeCell Identification Registers 0-3 at 0x1FF0-0x1FFC 19shows the register bit assignments These registers cannot be read in the Reset state Following sections describe the smcpcellid RegistersSMC PrimeCell Identification Register 20 smcpcellid0 Register bit assignments Bits Name Function 22 smcpcellid2 Register bit assignments Bits Name Function 23 smcpcellid3 Register bit assignments Bits Name Function Programmer’s Model for Test Test registers are provided for integration testing SMC Integration Configuration Register at 0x1E00SMC integration test registers Lists the SMC integration test registers Integration Inputs Register at 0x1E04 Smcintinputs Register bit assignments Bits Name Function Integration Outputs Register at 0x1E08 State Device Driver Requirements Memory initialization SMC and memory initialization sheet 1 SMC and memory initialization sheet 2 Where = denotes the appropriate chip select SMC and memory initialization sheet 3 ARM DDI 0389B Signal Descriptions About the signals list Where Ahbc = AHB Configuration signals Table A-1lists the clock and reset signals Clocks and resetsName Type Source Description Destination AHB signals Table A-2lists the AHB signalsWhere = 0 or C, where C = Configuration Table A-2 AHB signals SMC memory interface signals Table A-3lists the SMC memory interface signals Table A-4lists the SMC miscellaneous signals SMC miscellaneous signalsTable A-4 SMC miscellaneous signals Low-power interface Table A-5lists the low-power interface signals Configuration signal Table A-6lists the configuration signalTable A-6 Configuration signal Name Source Description Type Destination Table A-7 Scan chain signals Table A-7lists the scan chain signalsScan chains ARM DDI 0389B Advanced High-performance Bus AHB Advanced Microcontroller Bus Architecture Amba See also Little-endian memory Advanced Peripheral Bus APB Incremented An 8-bit data itemData bus Multi-master operation Divisible by four See UnpredictableThat event resource is Unpredictable Other purposes Has been completed Written as 0 and read asRemapping Reserved Glossary-6