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SMC Networks AHB SRAM/NOR, PL241 manual 19 Synchronous burst read

Models: AHB SRAM/NOR PL241

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Figure 2-19 Synchronous burst read

Functional Overview

Figure 2-19shows a burst read with the smc_wait_0 output of the memory used to delay the transfer.

Note

•Synchronous memories have a configuration register enabling smc_wait_0 to be asserted either on the same clock cycle as the delayed data or a cycle earlier. The SMC only supports smc_wait_0 being asserted one cycle early, enabling smc_wait_0 to be initially sampled with the fed back clock and then with smc_mclk0 before being used by the FSM. This enables the easiest timing closure. Additionally, you must configure the memory for smc_wait_0 to be active LOW.

•In synchronous operation, the SMC relies on the smc_wait_0 signal being deasserted HIGH to indicate that the memory can finish the transfer. When in synchronous mode some memories do not deassert the smc_wait_0 signal during non-array read transfers. Non-array read transfers are typically status register reads. To avoid stalling the system with these memories, in synchronous mode you must not perform non-array read transfers with the memory and SMC.

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Figure 2-19 Synchronous burst read

ARM DDI 0389B

Copyright © 2006 ARM Limited. All rights reserved.

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SMC Networks AHB SRAM/NOR, PL241 manual 19 Synchronous burst read

Contents

Revision r0p1 PrimeCell AHB SRAM/NOR Memory Controller PL241Technical Reference Manual Technical Reference Manual PrimeCell AHB SRAM/NOR Memory Controller PL241Release Information Proprietary NoticePreface ContentsChapter IntroductionProgrammer’s Model for Test Signal DescriptionsDevice Driver Requirements Appendix AList of Tables Register summary List of Figures Synchronous burst read in multiplexed-mode About this manual on page PrefaceFeedback on page Copyright 2006 ARM Limited. All rights reservedAbout this manual Using this manualProduct revision status whereTypographical Timing diagrams on page Appendix A Signal DescriptionsConventions TypographicalSignals Timing diagramsSignal level Denotes global Advanced eXtensible Interface AXI signalsDenotes Advanced Peripheral Bus APB signals Denotes Advanced High-performance Bus AHB signalsAMBA 3 APB Protocol v1.0 Specification ARM IHI Prefix BFeedback on this manual FeedbackFeedback on this product Introduction ChapterAbout the AHB MC on page Supported devices on page Copyright 2006 ARM Limited. All rights reservedAHB interface on page AHB to APB bridge on page Clock domains on page Low-power interfaces on page1.1 About the AHB MC 1.1.2 AHB to APB bridge 1.1.1 AHB interface1.1.5 Low-power interfaces Pseudo Static Random Access Memory PSRAM1.1.3 SMC 1.1.4 Clock domainsCellular RAM 1.0, 64MB PSRAM, for example mt45w4mw16bfb7011us 1.2 Supported devicesIntel W18 series NOR FLASH, for example 28f128W18td ARM DDI 0389B IntroductionCopyright 2006 ARM Limited. All rights reserved Functional description on page Functional OverviewFunctional operation on page SMC functional operation on page Chapter2.1 Functional description Low-power interface on pageAHB interface AHB to APB bridge Clock domains on page 2.1.1 AHB interface2.1.4 Low-power interface smcmreset0n2.1.3 Clock domains AHB clock domainSMC interface on page APB slave interface on page 2.2 SMCMemory manager on page Memory interface on page Pad interface on page Figure 2-3 SMC block diagram2.2.2 APB slave interface 2.2.1 SMC interface2.2.3 Format 2.2.4 Memory manager2.2.7 Interrupts 2.2.6 Pad interfaceBroken bursts on page Bufferable bit of the HPROT signal on page Clock domain operation on page Low-power interface operation on pageAHB response signals on page Locked transfers on page Removal of AHB error response logic on pageBroken bursts Bufferable bit of the HPROT signalUndefined length INCR bursts Locked transfers AHB response signalsRead after write hazard detection buffer Registered HWDATA Removal of AHB error response logicBig-endian 32-bit mode 2.3.2 AHB to APB bridge operationFigure 2-6 AHBC memory map 2.3.3 Clock domain operationa request input domaincsyreq an acknowledge output domaincsysack 2.3.4 Low-power interface operationStatic memory clocking options an active output domaincactive Figure 2-9 Accepting requests Miscellaneous signals on page APB slave interface operation on page Operating states Clocking and resets on pageReset Power is applied to the device, and hresetn is held LOWReset to Ready Ready to ResetReady to Low-power Low-power to ReadyAHB domain ResetsMemory clock domain Synchronous clockingsmcuserconfig70 2.4.3 Miscellaneous signalssmcuserstatus70 smcagtm0syncsmcmsync0 Hazard handling SRAM memory accesses on pagesmcrstbypass smcuseebiMemory burst length on page Booting using the SRAM on page SRAM memory accessesStandard SRAM access Memory address shifting Memory burst alignment Memory burst length Booting using the SRAMDirect commands on page Low-power operation Chip configuration registersLow-power operation Chip configuration registersDSEBLI Figure 2-11 Chip configuration registersPHPFBFIJ VHWF\FOHV VHWRSPRGH FKLSF\FOHV FKLSRSPRGHSoftware mechanism Direct commandsDevice pin mechanism Functional Overview Figure 2-12 Device pin mechanism6WDUW ULWHWLPLQJSDUDPHWHUV DQGRSHUDWLQJPRGHWR WKHPHPRU\FRQWUROOHU KROGLQJUHJLVWHUV ULWHUHTXLUHGHWHUQDOFKLSFunctional Overview Figure 2-13 Software mechanismCopyright 2006 ARM Limited. All rights reserved ARM DDI 0389BSRAM timing tables and diagrams They are divided into SRAM timing tables and diagrams2.4.7 Interrupts operation 2.4.8 Memory interface operationAsynchronous write on page Asynchronous read Asynchronous read in multiplexed-mode on pageAsynchronous write in multiplexed-mode on page Asynchronous page mode read on page Synchronous burst read on pageFigure 2-15 Asynchronous read in multiplexed-mode Figure 2-14 Asynchronous readAsynchronous read in multiplexed-mode smcdataout0310 output bus. Read data is accepted on the smcdatain0310 Asynchronous write in multiplexed-mode Table 2-10 Page read opmode chip register settingsFigure 2-17 Asynchronous write in multiplexed-mode Asynchronous page mode readMultiplexed-mode page accesses are not supported Figure 2-19 Synchronous burst read Figure 2-20 Synchronous burst read in multiplexed-mode Table 2-17 Synchronous burst write SRAM cycles register settings Table 2-16 Synchronous burst write opmode chip register settingsSynchronous burst write Figure 2-21 Synchronous burst writeFigure 2-22 Synchronous burst write in multiplexed-mode Reads followed by writes Writes followed by reads For tRC For tWC Copyright 2006 ARM Limited. All rights reserved Functional OverviewARM DDI 0389B 2-40About the programmer’s model on page Register summary on page Programmer’s ModelRegister descriptions on page ChapterSMC chip select configuration registers SMC configuration registersSMC user configuration registers 3.1 About the programmer’s modelFigure 3-2 SMC configuration register map 3.2 Register summaryFigure 3-3 SMC chip configuration register map Programmer’s ModelReset value Figure 3-4 SMC user configuration register mapName Base offsetTable 3-1 Register summary continued Reset valueName Base offset3.3.1 SMC Memory Controller Status Register at 3.3 Register descriptionsFigure 3-7 smcmemifcfg Register bit assignments 3.3.2 SMC Memory Interface Configuration Register atTable 3-3 smcmemifcfg Register bit assignments BitsTable 3-3 smcmemifcfg Register bit assignments continued 3.3.3 SMC Set Configuration Register atBits 3.3.4 SMC Clear Configuration Register at 0x100CName Function3.3.5 SMC Direct Command Register at 3.3.6 SMC Set Cycles Register at Figure 3-12 smcsetopmode Register bit assignments 3.3.7 SMC Set Opmode Register atBits Table 3-8 lists the register bit assignmentsName FunctionTable 3-8 smcsetopmode Register bit assignments continued Configuration Register at 0x1004 on pageBits Name3.3.9 SMC SRAM Cycles Registers 0-3 at 0x1100, 0x1120, 0x1140 3.3.8 SMC Refresh Period 0 Register at3.3.10 SMC Opmode Registers 0-3 at 0x1104, 0x1124, 0x1144 Bits Table 3-11 lists the register bit assignmentsName FunctionTable 3-12 lists the register bit assignments 3.3.11 SMC User Status Register atTable 3-11 smcopmode Register bit assignments continued Bits3.3.13 SMC Peripheral Identification Registers 0-3 at 0x1FE0-0x1FEC 3.3.12 SMC User Configuration Register atTable 3-13 lists the register bit assignments SMC Peripheral Identification Register 1 on page SMC Peripheral Identification RegisterSMC Peripheral Identification Register 2 on page SMC Peripheral Identification Register 3 on pageSMC Peripheral Identification Register SMC Peripheral Identification RegisterSMC Peripheral Identification Register Table 3-18 smcperiphid3 Register bit assignments3.3.14 SMC PrimeCell Identification Registers 0-3 at 0x1FF0-0x1FFC SMC PrimeCell Identification Register 2 on page SMC PrimeCell Identification RegisterSMC PrimeCell Identification Register 3 on page SMC PrimeCell Identification RegisterSMC PrimeCell Identification Register SMC PrimeCell Identification RegisterThe smcpcellid2 Register is hard-coded and the fields within the register indicate the value. Table 3-22 lists the register bit assignments SMC integration test registers on page Programmer’s Model for TestChapter Copyright 2006 ARM Limited. All rights reserved4.1 SMC integration test registers 4.1.1 SMC Integration Configuration Register at 0x1E00Integration Inputs Register at 0x1E04 4.1.2Table 4-3 smcintinputs Register bit assignments continued 4.1.3 Integration Outputs Register at 0x1E08Bits NameMemory initialization on page Device Driver RequirementsChapter Copyright 2006 ARM Limited. All rights reserved5.1 Memory initialization 6WDUW QLWLDOLHYDULDEOHV ULWHWLPLQJLQIRUPDWLRQ WRVPFBVHWBF\FOHV Figure 5-1 SMC and memory initialization sheet 1 ofKROGLQJ5HJLVWHU ULWHRSHUDWLQJPRGH LQIRUPDWLRQWR VPFBVHWBRSPRGH KROGLQJ5HJLVWHUDevice Driver Requirements Figure 5-2 SMC and memory initialization sheet 2 of6KHHW V PHPRU\GHYLFH 0RGH5HJDFFHVVHGE\ RUDGGUHVV RQO\Device Driver Requirements Figure 5-3 SMC and memory initialization sheet 3 of6KHHW 9HULI\ WKHQHZWLPLQJV DQGRSHUDWLQJ PRGH HV KHFNIRUFRUUHFW VPFBVUDPBF\FOHVB 5HJLVWHUFRQWHQWVARM DDI 0389B Device Driver RequirementsCopyright 2006 ARM Limited. All rights reserved About the signals list on page A-2 Clocks and resets on page A-3 Signal DescriptionsAHB signals on page A-4 SMC memory interface signals on page A-5 SMC miscellaneous signals on page A-6 Low-power interface on page A-7Figure A-1 AHB MC PL241 grouping of signals A.1 About the signals listSignal Descriptions ORFNVName A.2 Clocks and resetsType SourceTable A-2 AHB signals AHB signalsName TypeTable A-3 SMC memory interface signals A.4 SMC memory interface signalsName TypeTable A-4 SMC miscellaneous signals A.5 SMC miscellaneous signalsName TypeName A.6 Low-power interfaceType SourceTable A-6 Configuration signal A.7 Configuration signalSignal Descriptions NameTable A-7 Scan chain signals A.8 Scan chainsName TypeA-10 Signal DescriptionsCopyright 2006 ARM Limited. All rights reserved ARM DDI 0389BGlossary See Advanced Microcontroller Bus Architecture See Advanced High-performance BusSee Advanced Peripheral Bus comprises four beatsincremented See also BeatSee Should Be One to enable you to access selected parts of the deviceSee Should Be Zero See Should Be Zero or Preservedhas been completed Glossary-6 GlossaryCopyright 2006 ARM Limited. All rights reserved ARM DDI 0389B