Table A-2lists the AHB signals | SMC Networks PL241 specs

Signal Descriptions

A.3	AHB signals
	Table A-2lists the AHB signals.
					Table A-2 AHB signals

		Name	Type	Source/	Description
		Name	Type	destination	Description
				destination

		hsel<x>	Input	AHB	Transfer is to this port

		haddr<x>[31:0]	Input	AHB	Address of transfer

		htrans<x>[1:0]	Input	AHB	Transfer type

		hwrite<x>	Input	AHB	Transfer is write or read

		hsize<x>[2:0]	Input	AHB	Size of transfer

		hburst<x>[2:0]	Input	AHB	Burst type of transfer

		hprot<x>[3:0]	Input	AHB	Protection of transfer

		hwdata<x>[31:0]	Input	AHB	Write data

		hmastlock<x>	Input	AHB	Locked transfer

		hready<x>	Input	AHB	System ready

		hrdata<x>[31:0]	Output	AHB	Read data

		hreadyout<x>	Output	AHB	Slave ready

		hresp<x>[1:0]	Output	AHB	Slave response

where:

<x> = 0 or C, where C = Configuration.

A-4

Copyright © 2006 ARM Limited. All rights reserved.

ARM DDI 0389B

Image 98

SMC Networks PL241 Table A-2lists the AHB signals, Where = 0 or C, where C = Configuration, Table A-2 AHB signals

Contents

PrimeCell AHB SRAM/NOR Memory Controller PL241 Copyright 2006 ARM Limited. All rights reserved PrimeCell AHB SRAM/NOR Memory Controller PL241Technical Reference Manual Contents Chapter Programmer’s Model for Test List of Tables List of Tables List of Figures Figure A-1 AHB MC PL241 grouping of signals Preface Feedback on Product revision status Using this manualAbout this manual Intended audience Bold ConventionsTypographical Timing diagrams Signals ARM publications NumberingFurther reading Feedback on this manual FeedbackFeedback on this product Introduction SMC on About the AHB MCThis section describes AHB interface AHB to APB bridge Clock domains Low-power interfaces3 SMC Supported devices Intel W18 series NOR FLASH, for example 28f128W18td Introduction Copyright 2006 ARM Limited. All rights reserved Functional Overview Functional description This section is divided into AHB clock domain Smcmreset0nLow-power interface Static memory clock domain Format on SMCMain blocks of the SMC are Interrupts on Format SMC interfaceAPB slave interface Memory manager Pad interface Interrupts AHB fixed burst types Functional operationAHB interface operation Broken bursts Bufferable bit of the Hprot signalUndefined length Incr bursts Locked transfers AHB response signalsRead after write hazard detection buffer Registered Hwdata Big-endian 32-bit modeRemoval of AHB error response logic AHB to APB bridge operation Clock domain operation Ahbc memory map 1lists the static memory clocking options Low-power interface operationStatic memory clocking options Static memory clocking options Where Domain is ahb or smc An active output Domaincactive Accepting requests SMC states are as follows SMC functional operationOperating states Clocking and resets Clocking Resets Smcuserstatus70 Miscellaneous signalsSmcuserconfig70 Smcagtm0sync Hazard handling APB slave interface operationFormat block Sram memory accesses Memory burst length Memory manager operation Low-power operationChip configuration registers 11 Chip configuration registers Software mechanism Direct commandsDevice pin mechanism 12 Device pin mechanism 13 Software mechanism Memory interface operation Sram timing tables and diagramsInterrupts operation Asynchronous read opmode chip register settings Asynchronous read Sram cycles register settings 4and -5list the smcopmode00-3 and Sram Register settings 14 Asynchronous read Asynchronous write Sram cycles register settings 6and -7list the smcopmode00-3 and Sram Register settingsAsynchronous write opmode chip register settings 10 Page read opmode chip register settings 8and -9list the smcopmode00-3 and Sram Register settings10and -11list the smcopmode00-3 and Sram Register settings 13 Synchronous burst read Sram cycles register settings 12and -13list the smcopmode00-3 and Sram Register settings12 Synchronous burst read opmode chip register settings 19 Synchronous burst read 14and -15list the smcopmode00-3 and Sram Register settings 20 Synchronous burst read in multiplexed-mode 17 Synchronous burst write Sram cycles register settings 16and -17list the smcopmode00-3 and Sram Register settings16 Synchronous burst write opmode chip register settings 18and -19list the smcopmode00-3 and Sram Register settings 22 Synchronous burst write in multiplexed-mode 20and -21list the smcopmode00-3 and Sram Register settings B0100 B0110 B001 TCEOE is only required if wait is asserted when oen goes LOW TWC = ARM DDI 0389B Programmer’s Model About the programmer’s model 2shows the SMC configuration register map Register summary Name Base offset Type Reset value Description 1lists the SMC Registers Register summary SMC Memory Controller Status Register at Register descriptionsThis section describes the SMC registers 2lists the register bit assignments Bits Name Function SMC Memory Interface Configuration Register at3lists the register bit assignments SMC Set Configuration Register at Smcmemccfgset Register bit assignments 5lists the register bit assignments SMC Clear Configuration Register at 0x100C4lists the register bit assignments Smcmemccfgclr Register bit assignments Bits Name Function Smcdirectcmd Register bit assignments SMC Direct Command Register at6lists the register bit assignments SMC Set Cycles Register at Lists the register bit assignments SMC Set Opmode Register at 12 smcsetopmode Register bit assignments 8lists the register bit assignments Smcsetopmode Register bit assignments Memory width mw field Smcrefreshperiod0 Register bit assignments SMC Refresh Period 0 Register atSMC Sram Cycles Registers 0-3 at 0x1100, 0x1120, 0x1140 10lists the register bit assignments SMC Opmode Registers 0-3 at 0x1104, 0x1124, 0x1144 11lists the register bit assignments 11 smcopmode Register bit assignments SMC User Status Register at12lists the register bit assignments 12 smcuserstatus Register bit assignments 13 lists the register bit assignments SMC User Configuration Register at13 smcuserconfig Register bit assignments Bits Name Description 15 smcperiphid0 Register bit assignments Bits Name Function Following section describe the smcperiphid RegistersSMC Peripheral Identification Register 16 smcperiphid1 Register bit assignments Bits Name Function 17 smcperiphid2 Register bit assignments Bits Name Function SMC PrimeCell Identification Registers 0-3 at 0x1FF0-0x1FFC 19shows the register bit assignments SMC PrimeCell Identification Register These registers cannot be read in the Reset stateFollowing sections describe the smcpcellid Registers 20 smcpcellid0 Register bit assignments Bits Name Function 22 smcpcellid2 Register bit assignments Bits Name Function 23 smcpcellid3 Register bit assignments Bits Name Function Programmer’s Model for Test SMC integration test registers Test registers are provided for integration testingSMC Integration Configuration Register at 0x1E00 Lists the SMC integration test registers Integration Inputs Register at 0x1E04 Smcintinputs Register bit assignments Bits Name Function Integration Outputs Register at 0x1E08 State Device Driver Requirements Memory initialization SMC and memory initialization sheet 1 SMC and memory initialization sheet 2 Where = denotes the appropriate chip select SMC and memory initialization sheet 3 ARM DDI 0389B Signal Descriptions About the signals list Where Ahbc = AHB Configuration signals Name Type Source Description Destination Clocks and resetsTable A-1lists the clock and reset signals Where = 0 or C, where C = Configuration AHB signalsTable A-2lists the AHB signals Table A-2 AHB signals SMC memory interface signals Table A-3lists the SMC memory interface signals Table A-4 SMC miscellaneous signals SMC miscellaneous signalsTable A-4lists the SMC miscellaneous signals Low-power interface Table A-5lists the low-power interface signals Table A-6 Configuration signal Configuration signalTable A-6lists the configuration signal Name Source Description Type Destination Scan chains Table A-7lists the scan chain signalsTable A-7 Scan chain signals ARM DDI 0389B Advanced High-performance Bus AHB Advanced Microcontroller Bus Architecture Amba See also Little-endian memory Advanced Peripheral Bus APB Data bus IncrementedAn 8-bit data item Multi-master operation That event resource is Unpredictable Divisible by fourSee Unpredictable Other purposes Remapping Has been completedWritten as 0 and read as Reserved Glossary-6