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Introduction
1.1.3SMC
The SMC is a
The SMC is
•the SRAM memory type
•the number of SRAM memory devices
•the maximum SRAM memory width.
The SRAM memory interface type is defined as supporting:
•synchronous or asynchronous SRAM
•Pseudo Static Random Access Memory (PSRAM)
•NOR flash
•NAND flash devices with an SRAM interface.
The SMC block offers the following features:
•it is configured to support the maximum SRAM memory data width of
•programmable cycle timings, and memory width per chip select
•atomic switching of memory device and controller operating modes
•support for the PL220 External Bus Interface (EBI) PrimeCell, enabling sharing of external address and data bus pins between memory controller interfaces
•support for a
•support for a remap signal
•support for clock domains to be synchronous or asynchronous
See Chapter 2 Functional Overview for more information.
1.1.4Clock domains
The memory controller has two clock domains:
•AHB clock domain
•static memory clock domain.
See Chapter 2 Functional Overview for more information.
1.1.5Low-power interfaces
The memory controller has two
See Chapter 2 Functional Overview for more information.
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