Manuals / SMC Networks / Computer Equipment / Network Card

SMC Networks PL241 SMC User Status Register at, 12 lists the register bit assignments, Bits, Name

Models: AHB SRAM/NOR PL241

1 110

Download 110 pages 44.4 Kb

Page 78

Table 3-11 smc_opmode Register bit assignments (continued)

Programmer’s Model

				Table 3-11 smc_opmode Register bit assignments (continued)

Bits	Name	Function

[6]	wr_sync	When set, the memory operates in write sync mode.

[5:3]	rd_bl	Determines the memory burst lengths for reads:
		b000		= 1 beat
		b001		= 4 beats
		b010		= 8 beats
		b011		= 16 beats
		b100		= 32 beats
		b101		= continuous
		b110-b111 = reserved.

[2]	rd_sync	When set, the memory operates in read sync mode.

[1:0]	mw	Determines the SMC memory data bus width:
		b00	= 8 bits
		b01	= 16 bits
		b10	= 32 bits
		b11	= reserved.

3.3.11SMC User Status Register at 0x1200

The smc_user_status Register is a general purpose read-only register that returns the state on the smc_user_status[7:0] primary inputs. The smc_user_status Register can be read in all states. Figure 3-16shows the register bit assignments.

8QGHILQHG

VPFBXVHUBVWDWXV

		Figure 3-16 smc_user_status Register bit assignments
	Table 3-12lists the register bit assignments.
		Table 3-12 smc_user_status Register bit assignments
Bits	Name	Function
[31:8]	-	Reserved, read undefined
[7:0]	smc_user_status	The value returns the state of the smc_user_status[7:0] primary input pins

3-18

Copyright © 2006 ARM Limited. All rights reserved.

ARM DDI 0389B

Image 78

SMC Networks PL241, AHB SRAM/NOR SMC User Status Register at, 12 lists the register bit assignments, Bits, Name, Function

Contents

PrimeCell AHB SRAM/NOR Memory Controller PL241 Technical Reference ManualRevision r0p1 Release Information PrimeCell AHB SRAM/NOR Memory Controller PL241Technical Reference Manual Proprietary NoticeChapter ContentsPreface IntroductionDevice Driver Requirements Signal DescriptionsProgrammer’s Model for Test Appendix AList of Tables Register summary List of Figures Synchronous burst read in multiplexed-mode Preface About this manual on pageFeedback on page Product revision status Using this manualAbout this manual whereConventions Appendix A Signal DescriptionsTypographical Timing diagrams on page TypographicalSignal level Timing diagramsSignals Denotes global Advanced eXtensible Interface AXI signalsAMBA 3 APB Protocol v1.0 Specification ARM IHI Denotes Advanced High-performance Bus AHB signalsDenotes Advanced Peripheral Bus APB signals Prefix BFeedback Feedback on this productFeedback on this manual Chapter IntroductionAbout the AHB MC on page Supported devices on page Clock domains on page Low-power interfaces on page 1.1 About the AHB MCAHB interface on page AHB to APB bridge on page 1.1.1 AHB interface 1.1.2 AHB to APB bridge1.1.3 SMC Pseudo Static Random Access Memory PSRAM1.1.5 Low-power interfaces 1.1.4 Clock domains1.2 Supported devices Intel W18 series NOR FLASH, for example 28f128W18tdCellular RAM 1.0, 64MB PSRAM, for example mt45w4mw16bfb7011us Introduction Functional Overview Functional description on pageFunctional operation on page SMC functional operation on page AHB interface AHB to APB bridge Clock domains on page Low-power interface on page2.1 Functional description 2.1.1 AHB interface2.1.3 Clock domains smcmreset0n2.1.4 Low-power interface AHB clock domainMemory manager on page Memory interface on page Pad interface on page 2.2 SMCSMC interface on page APB slave interface on page Figure 2-3 SMC block diagram2.2.3 Format 2.2.1 SMC interface2.2.2 APB slave interface 2.2.4 Memory manager2.2.6 Pad interface 2.2.7 InterruptsAHB response signals on page Locked transfers on page Clock domain operation on page Low-power interface operation on pageBroken bursts on page Bufferable bit of the HPROT signal on page Removal of AHB error response logic on pageBufferable bit of the HPROT signal Undefined length INCR burstsBroken bursts AHB response signals Read after write hazard detection bufferLocked transfers Big-endian 32-bit mode Removal of AHB error response logicRegistered HWDATA 2.3.2 AHB to APB bridge operation2.3.3 Clock domain operation Figure 2-6 AHBC memory map2.3.4 Low-power interface operation Static memory clocking optionsa request input domaincsyreq an acknowledge output domaincsysack an active output domaincactive Figure 2-9 Accepting requests Reset Operating states Clocking and resets on pageMiscellaneous signals on page APB slave interface operation on page Power is applied to the device, and hresetn is held LOWReady to Low-power Ready to ResetReset to Ready Low-power to ReadyMemory clock domain ResetsAHB domain Synchronous clockingsmcuserstatus70 2.4.3 Miscellaneous signalssmcuserconfig70 smcagtm0syncsmcrstbypass Hazard handling SRAM memory accesses on pagesmcmsync0 smcuseebiSRAM memory accesses Standard SRAM access Memory address shifting Memory burst alignmentMemory burst length on page Booting using the SRAM on page Booting using the SRAM Memory burst lengthLow-power operation Low-power operation Chip configuration registersDirect commands on page Chip configuration registersPHPFBFIJ VHWF\FOHV VHWRSPRGH Figure 2-11 Chip configuration registersDSEBLI FKLSF\FOHV FKLSRSPRGHDirect commands Device pin mechanismSoftware mechanism WKHPHPRU\FRQWUROOHU KROGLQJUHJLVWHUV ULWHUHTXLUHGHWHUQDOFKLS Figure 2-12 Device pin mechanism6WDUW ULWHWLPLQJSDUDPHWHUV DQGRSHUDWLQJPRGHWR VHOHFWQXPEHUDQGUHTXLUHG PRGHUHJLVWHUYDOXHWRWKHFigure 2-13 Software mechanism 2.4.7 Interrupts operation They are divided into SRAM timing tables and diagramsSRAM timing tables and diagrams 2.4.8 Memory interface operationAsynchronous write in multiplexed-mode on page Asynchronous read Asynchronous read in multiplexed-mode on pageAsynchronous write on page Asynchronous page mode read on page Synchronous burst read on pageFigure 2-14 Asynchronous read Asynchronous read in multiplexed-modeFigure 2-15 Asynchronous read in multiplexed-mode smcdataout0310 output bus. Read data is accepted on the smcdatain0310 Figure 2-17 Asynchronous write in multiplexed-mode Table 2-10 Page read opmode chip register settingsAsynchronous write in multiplexed-mode Asynchronous page mode readMultiplexed-mode page accesses are not supported Figure 2-19 Synchronous burst read Figure 2-20 Synchronous burst read in multiplexed-mode Synchronous burst write Table 2-16 Synchronous burst write opmode chip register settingsTable 2-17 Synchronous burst write SRAM cycles register settings Figure 2-21 Synchronous burst writeFigure 2-22 Synchronous burst write in multiplexed-mode Reads followed by writes Writes followed by reads For tRC For tWC 2-40 Programmer’s Model About the programmer’s model on page Register summary on pageRegister descriptions on page SMC user configuration registers SMC configuration registersSMC chip select configuration registers 3.1 About the programmer’s modelFigure 3-3 SMC chip configuration register map 3.2 Register summaryFigure 3-2 SMC configuration register map VPFBUHIUHVKBSHULRGB Name Figure 3-4 SMC user configuration register mapReset value Base offsetTable 3-1 Register summary continued 3.3 Register descriptions 3.3.1 SMC Memory Controller Status Register at3.3.2 SMC Memory Interface Configuration Register at Figure 3-7 smcmemifcfg Register bit assignmentsTable 3-3 smcmemifcfg Register bit assignments 3.3.3 SMC Set Configuration Register at Table 3-3 smcmemifcfg Register bit assignments continued3.3.4 SMC Clear Configuration Register at 0x100C Figure 3-9 smcmemccfgclr Register bit assignmentsTable 3-5 smcmemccfgclr Register bit assignments 3.3.5 SMC Direct Command Register at 3.3.6 SMC Set Cycles Register at 3.3.7 SMC Set Opmode Register at Figure 3-12 smcsetopmode Register bit assignmentsTable 3-8 lists the register bit assignments Table 3-8 smcsetopmode Register bit assignmentsConfiguration Register at 0x1004 on page Table 3-8 smcsetopmode Register bit assignments continuedmemory width mw field 3.3.8 SMC Refresh Period 0 Register at 3.3.9 SMC SRAM Cycles Registers 0-3 at 0x1100, 0x1120, 0x11403.3.10 SMC Opmode Registers 0-3 at 0x1104, 0x1124, 0x1144 Table 3-11 lists the register bit assignments Table 3-11 smcopmode Register bit assignmentsTable 3-11 smcopmode Register bit assignments continued 3.3.11 SMC User Status Register atTable 3-12 lists the register bit assignments Figure 3-16 smcuserstatus Register bit assignments3.3.12 SMC User Configuration Register at Table 3-13 lists the register bit assignments3.3.13 SMC Peripheral Identification Registers 0-3 at 0x1FE0-0x1FEC SMC Peripheral Identification Register 2 on page SMC Peripheral Identification RegisterSMC Peripheral Identification Register 1 on page SMC Peripheral Identification Register 3 on pageTable 3-18 smcperiphid3 Register bit assignments 3.3.14 SMC PrimeCell Identification Registers 0-3 at 0x1FF0-0x1FFC SMC PrimeCell Identification Register 3 on page SMC PrimeCell Identification RegisterSMC PrimeCell Identification Register 2 on page SMC PrimeCell Identification RegisterThe smcpcellid2 Register is hard-coded and the fields within the register indicate the value. Table 3-22 lists the register bit assignments Programmer’s Model for Test SMC integration test registers on page4.1.1 SMC Integration Configuration Register at 0x1E00 4.1 SMC integration test registers4.1.2 Integration Inputs Register at 0x1E04Figure 4-4 smcintoutputs Register bit assignments 4.1.3 Integration Outputs Register at 0x1E08Table 4-3 smcintinputs Register bit assignments continued Table 4-4 smcintoutputs Register bit assignmentsDevice Driver Requirements Memory initialization on page5.1 Memory initialization KROGLQJ5HJLVWHU ULWHRSHUDWLQJPRGH LQIRUPDWLRQWR VPFBVHWBRSPRGH Figure 5-1 SMC and memory initialization sheet 1 of6WDUW QLWLDOLHYDULDEOHV ULWHWLPLQJLQIRUPDWLRQ WRVPFBVHWBF\FOHV KROGLQJ5HJLVWHURUDGGUHVV RQO\ Figure 5-2 SMC and memory initialization sheet 2 of6KHHW V PHPRU\GHYLFH 0RGH5HJDFFHVVHGE\ ZULWLQJFRPPDQG LQIRUPDWLRQWR VPFBGLUHFWBFPGKHFNIRUFRUUHFW VPFBVUDPBF\FOHVB 5HJLVWHUFRQWHQWV Figure 5-3 SMC and memory initialization sheet 3 of6KHHW 9HULI\ WKHQHZWLPLQJV DQGRSHUDWLQJ PRGH HV KHFNIRUFRUUHFW VPFBRSPRGHB 5HJLVWHUFRQWHQWVDevice Driver Requirements AHB signals on page A-4 SMC memory interface signals on page A-5 Signal DescriptionsAbout the signals list on page A-2 Clocks and resets on page A-3 SMC miscellaneous signals on page A-6 Low-power interface on page A-7Signal Descriptions A.1 About the signals listFigure A-1 AHB MC PL241 grouping of signals ORFNVA.2 Clocks and resets Sourcedestination AHB signals Table A-2 AHB signalsA.4 SMC memory interface signals Table A-3 SMC memory interface signalsA.5 SMC miscellaneous signals Table A-4 SMC miscellaneous signalsA.6 Low-power interface A.7 Configuration signal Table A-6 Configuration signalA.8 Scan chains Table A-7 Scan chain signalsA-10 Glossary See Advanced Peripheral Bus See Advanced High-performance BusSee Advanced Microcontroller Bus Architecture comprises four beatsSee also Beat incrementedSee Should Be Zero to enable you to access selected parts of the deviceSee Should Be One See Should Be Zero or Preservedhas been completed Glossary-6