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SMC Networks PL241 See Advanced High-performance Bus, See Advanced Peripheral Bus, See also Burst

Models: AHB SRAM/NOR PL241

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Glossary

Advanced Peripheral Bus (APB)

A simpler bus protocol than AHB. It is designed for use with ancillary or general-purpose peripherals such as timers, interrupt controllers, UARTs, and I/O ports. Connection to the main system bus is through a system-to-peripheral bus bridge that helps to reduce system power consumption.

AHB	See Advanced High-performance Bus.
Aligned	A data item stored at an address that is divisible by the number of bytes that defines the
	data size is said to be aligned. Aligned words and halfwords have addresses that are
	divisible by four and two respectively. The terms word-aligned and halfword-aligned
	therefore stipulate addresses that are divisible by four and two respectively.
AMBA	See Advanced Microcontroller Bus Architecture.
APB	See Advanced Peripheral Bus.
Beat	Alternative word for an individual transfer within a burst. For example, an INCR4 burst
	comprises four beats.
	See also Burst.
BE-8	Big-endian view of memory in a byte-invariant system.
	See also BE-32, LE, Byte-invariant and Word-invariant.
BE-32	Big-endian view of memory in a word-invariant system.
	See also BE-8, LE, Byte-invariant and Word-invariant.
Big-endian	Byte ordering scheme in which bytes of decreasing significance in a data word are
	stored at increasing addresses in memory.
	See also Little-endian and Endianness.
Big-endian memory	Memory in which:
	•	a byte or halfword at a word-aligned address is the most significant byte or
		halfword within the word at that address
	•	a byte at a halfword-aligned address is the most significant byte within the
		halfword at that address.

See also Little-endian memory.

Glossary-2

Copyright © 2006 ARM Limited. All rights reserved.

ARM DDI 0389B

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SMC Networks PL241 See Advanced High-performance Bus, See Advanced Microcontroller Bus Architecture, comprises four beats

Contents

Technical Reference Manual PrimeCell AHB SRAM/NOR Memory Controller PL241Revision r0p1 Release Information PrimeCell AHB SRAM/NOR Memory Controller PL241Technical Reference Manual Proprietary NoticeChapter ContentsPreface IntroductionDevice Driver Requirements Signal DescriptionsProgrammer’s Model for Test Appendix AList of Tables Register summary List of Figures Synchronous burst read in multiplexed-mode Feedback on page PrefaceAbout this manual on page Copyright 2006 ARM Limited. All rights reservedProduct revision status Using this manualAbout this manual whereConventions Appendix A Signal DescriptionsTypographical Timing diagrams on page TypographicalSignal level Timing diagramsSignals Denotes global Advanced eXtensible Interface AXI signalsAMBA 3 APB Protocol v1.0 Specification ARM IHI Denotes Advanced High-performance Bus AHB signalsDenotes Advanced Peripheral Bus APB signals Prefix BFeedback on this product FeedbackFeedback on this manual About the AHB MC on page Supported devices on page ChapterIntroduction Copyright 2006 ARM Limited. All rights reserved1.1 About the AHB MC Clock domains on page Low-power interfaces on pageAHB interface on page AHB to APB bridge on page 1.1.1 AHB interface 1.1.2 AHB to APB bridge1.1.3 SMC Pseudo Static Random Access Memory PSRAM1.1.5 Low-power interfaces 1.1.4 Clock domainsIntel W18 series NOR FLASH, for example 28f128W18td 1.2 Supported devicesCellular RAM 1.0, 64MB PSRAM, for example mt45w4mw16bfb7011us Copyright 2006 ARM Limited. All rights reserved IntroductionARM DDI 0389B Functional operation on page SMC functional operation on page Functional OverviewFunctional description on page ChapterAHB interface AHB to APB bridge Clock domains on page Low-power interface on page2.1 Functional description 2.1.1 AHB interface2.1.3 Clock domains smcmreset0n2.1.4 Low-power interface AHB clock domainMemory manager on page Memory interface on page Pad interface on page 2.2 SMCSMC interface on page APB slave interface on page Figure 2-3 SMC block diagram2.2.3 Format 2.2.1 SMC interface2.2.2 APB slave interface 2.2.4 Memory manager2.2.6 Pad interface 2.2.7 InterruptsAHB response signals on page Locked transfers on page Clock domain operation on page Low-power interface operation on pageBroken bursts on page Bufferable bit of the HPROT signal on page Removal of AHB error response logic on pageUndefined length INCR bursts Bufferable bit of the HPROT signalBroken bursts Read after write hazard detection buffer AHB response signalsLocked transfers Big-endian 32-bit mode Removal of AHB error response logicRegistered HWDATA 2.3.2 AHB to APB bridge operation2.3.3 Clock domain operation Figure 2-6 AHBC memory mapStatic memory clocking options 2.3.4 Low-power interface operationa request input domaincsyreq an acknowledge output domaincsysack an active output domaincactive Figure 2-9 Accepting requests Reset Operating states Clocking and resets on pageMiscellaneous signals on page APB slave interface operation on page Power is applied to the device, and hresetn is held LOWReady to Low-power Ready to ResetReset to Ready Low-power to ReadyMemory clock domain ResetsAHB domain Synchronous clockingsmcuserstatus70 2.4.3 Miscellaneous signalssmcuserconfig70 smcagtm0syncsmcrstbypass Hazard handling SRAM memory accesses on pagesmcmsync0 smcuseebiStandard SRAM access Memory address shifting Memory burst alignment SRAM memory accessesMemory burst length on page Booting using the SRAM on page Booting using the SRAM Memory burst lengthLow-power operation Low-power operation Chip configuration registersDirect commands on page Chip configuration registersPHPFBFIJ VHWF\FOHV VHWRSPRGH Figure 2-11 Chip configuration registersDSEBLI FKLSF\FOHV FKLSRSPRGHDevice pin mechanism Direct commandsSoftware mechanism 6WDUW ULWHWLPLQJSDUDPHWHUV DQGRSHUDWLQJPRGHWR Figure 2-12 Device pin mechanismFunctional Overview WKHPHPRU\FRQWUROOHU KROGLQJUHJLVWHUV ULWHUHTXLUHGHWHUQDOFKLSCopyright 2006 ARM Limited. All rights reserved Figure 2-13 Software mechanismFunctional Overview ARM DDI 0389B2.4.7 Interrupts operation They are divided into SRAM timing tables and diagramsSRAM timing tables and diagrams 2.4.8 Memory interface operationAsynchronous write in multiplexed-mode on page Asynchronous read Asynchronous read in multiplexed-mode on pageAsynchronous write on page Asynchronous page mode read on page Synchronous burst read on pageAsynchronous read in multiplexed-mode Figure 2-14 Asynchronous readFigure 2-15 Asynchronous read in multiplexed-mode smcdataout0310 output bus. Read data is accepted on the smcdatain0310 Figure 2-17 Asynchronous write in multiplexed-mode Table 2-10 Page read opmode chip register settingsAsynchronous write in multiplexed-mode Asynchronous page mode readMultiplexed-mode page accesses are not supported Figure 2-19 Synchronous burst read Figure 2-20 Synchronous burst read in multiplexed-mode Synchronous burst write Table 2-16 Synchronous burst write opmode chip register settingsTable 2-17 Synchronous burst write SRAM cycles register settings Figure 2-21 Synchronous burst writeFigure 2-22 Synchronous burst write in multiplexed-mode Reads followed by writes Writes followed by reads For tRC For tWC ARM DDI 0389B Functional OverviewCopyright 2006 ARM Limited. All rights reserved 2-40Register descriptions on page Programmer’s ModelAbout the programmer’s model on page Register summary on page ChapterSMC user configuration registers SMC configuration registersSMC chip select configuration registers 3.1 About the programmer’s modelFigure 3-3 SMC chip configuration register map 3.2 Register summaryFigure 3-2 SMC configuration register map Programmer’s ModelName Figure 3-4 SMC user configuration register mapReset value Base offsetName Reset valueTable 3-1 Register summary continued Base offset3.3 Register descriptions 3.3.1 SMC Memory Controller Status Register atTable 3-3 smcmemifcfg Register bit assignments 3.3.2 SMC Memory Interface Configuration Register atFigure 3-7 smcmemifcfg Register bit assignments Bits3.3.3 SMC Set Configuration Register at Table 3-3 smcmemifcfg Register bit assignments continuedName 3.3.4 SMC Clear Configuration Register at 0x100CBits Function3.3.5 SMC Direct Command Register at 3.3.6 SMC Set Cycles Register at 3.3.7 SMC Set Opmode Register at Figure 3-12 smcsetopmode Register bit assignmentsName Table 3-8 lists the register bit assignmentsBits FunctionBits Configuration Register at 0x1004 on pageTable 3-8 smcsetopmode Register bit assignments continued Name3.3.8 SMC Refresh Period 0 Register at 3.3.9 SMC SRAM Cycles Registers 0-3 at 0x1100, 0x1120, 0x11403.3.10 SMC Opmode Registers 0-3 at 0x1104, 0x1124, 0x1144 Name Table 3-11 lists the register bit assignmentsBits FunctionTable 3-11 smcopmode Register bit assignments continued 3.3.11 SMC User Status Register atTable 3-12 lists the register bit assignments BitsTable 3-13 lists the register bit assignments 3.3.12 SMC User Configuration Register at3.3.13 SMC Peripheral Identification Registers 0-3 at 0x1FE0-0x1FEC SMC Peripheral Identification Register 2 on page SMC Peripheral Identification RegisterSMC Peripheral Identification Register 1 on page SMC Peripheral Identification Register 3 on pageSMC Peripheral Identification Register SMC Peripheral Identification RegisterSMC Peripheral Identification Register Table 3-18 smcperiphid3 Register bit assignments3.3.14 SMC PrimeCell Identification Registers 0-3 at 0x1FF0-0x1FFC SMC PrimeCell Identification Register 3 on page SMC PrimeCell Identification RegisterSMC PrimeCell Identification Register 2 on page SMC PrimeCell Identification RegisterThe smcpcellid2 Register is hard-coded and the fields within the register indicate the value. Table 3-22 lists the register bit assignments SMC PrimeCell Identification RegisterSMC PrimeCell Identification Register Chapter Programmer’s Model for TestSMC integration test registers on page Copyright 2006 ARM Limited. All rights reserved4.1.1 SMC Integration Configuration Register at 0x1E00 4.1 SMC integration test registers4.1.2 Integration Inputs Register at 0x1E04Bits 4.1.3 Integration Outputs Register at 0x1E08Table 4-3 smcintinputs Register bit assignments continued NameChapter Device Driver RequirementsMemory initialization on page Copyright 2006 ARM Limited. All rights reserved5.1 Memory initialization KROGLQJ5HJLVWHU ULWHRSHUDWLQJPRGH LQIRUPDWLRQWR VPFBVHWBRSPRGH Figure 5-1 SMC and memory initialization sheet 1 of6WDUW QLWLDOLHYDULDEOHV ULWHWLPLQJLQIRUPDWLRQ WRVPFBVHWBF\FOHV KROGLQJ5HJLVWHU6KHHW V PHPRU\GHYLFH 0RGH5HJDFFHVVHGE\ Figure 5-2 SMC and memory initialization sheet 2 ofDevice Driver Requirements RUDGGUHVV RQO\6KHHW 9HULI\ WKHQHZWLPLQJV DQGRSHUDWLQJ PRGH HV Figure 5-3 SMC and memory initialization sheet 3 ofDevice Driver Requirements KHFNIRUFRUUHFW VPFBVUDPBF\FOHVB 5HJLVWHUFRQWHQWVCopyright 2006 ARM Limited. All rights reserved Device Driver RequirementsARM DDI 0389B AHB signals on page A-4 SMC memory interface signals on page A-5 Signal DescriptionsAbout the signals list on page A-2 Clocks and resets on page A-3 SMC miscellaneous signals on page A-6 Low-power interface on page A-7Signal Descriptions A.1 About the signals listFigure A-1 AHB MC PL241 grouping of signals ORFNVType A.2 Clocks and resetsName SourceName AHB signalsTable A-2 AHB signals TypeName A.4 SMC memory interface signalsTable A-3 SMC memory interface signals TypeName A.5 SMC miscellaneous signalsTable A-4 SMC miscellaneous signals TypeType A.6 Low-power interfaceName SourceSignal Descriptions A.7 Configuration signalTable A-6 Configuration signal NameName A.8 Scan chainsTable A-7 Scan chain signals TypeCopyright 2006 ARM Limited. All rights reserved Signal DescriptionsA-10 ARM DDI 0389BGlossary See Advanced Peripheral Bus See Advanced High-performance BusSee Advanced Microcontroller Bus Architecture comprises four beatsSee also Beat incrementedSee Should Be Zero to enable you to access selected parts of the deviceSee Should Be One See Should Be Zero or Preservedhas been completed Copyright 2006 ARM Limited. All rights reserved GlossaryGlossary-6 ARM DDI 0389B