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PL241 Device Driver Requirements, Copyright 2006 ARM Limited. All rights reserved
Models:
AHB SRAM/NOR
PL241
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Specs
Typographical Timing diagrams on page
smcuserconfig70
smcmreset0n
Direct commands on page
Removal of AHB error response logic on page
Signal Descriptions
10 Page read opmode chip register settings
Clock domains on page Low-power interfaces on page
to enable you to access selected parts of the device
Page 94
Image 94
Device Driver Requirements
5-6
Copyright © 2006 ARM Limited. All rights reserved.
ARM DDI 0389B
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Contents
Technical Reference Manual
PrimeCell AHB SRAM/NOR Memory Controller PL241
Revision r0p1
Release Information
PrimeCell AHB SRAM/NOR Memory Controller PL241
Technical Reference Manual
Proprietary Notice
Chapter
Contents
Preface
Introduction
Device Driver Requirements
Signal Descriptions
Programmer’s Model for Test
Appendix A
List of Tables
Register summary
List of Figures
Synchronous burst read in multiplexed-mode
Feedback on page
Preface
About this manual on page
Copyright 2006 ARM Limited. All rights reserved
Product revision status
Using this manual
About this manual
where
Conventions
Appendix A Signal Descriptions
Typographical Timing diagrams on page
Typographical
Signal level
Timing diagrams
Signals
Denotes global Advanced eXtensible Interface AXI signals
AMBA 3 APB Protocol v1.0 Specification ARM IHI
Denotes Advanced High-performance Bus AHB signals
Denotes Advanced Peripheral Bus APB signals
Prefix B
Feedback on this product
Feedback
Feedback on this manual
About the AHB MC on page Supported devices on page
Chapter
Introduction
Copyright 2006 ARM Limited. All rights reserved
1.1 About the AHB MC
Clock domains on page Low-power interfaces on page
AHB interface on page AHB to APB bridge on page
1.1.1 AHB interface
1.1.2 AHB to APB bridge
1.1.3 SMC
Pseudo Static Random Access Memory PSRAM
1.1.5 Low-power interfaces
1.1.4 Clock domains
Intel W18 series NOR FLASH, for example 28f128W18td
1.2 Supported devices
Cellular RAM 1.0, 64MB PSRAM, for example mt45w4mw16bfb7011us
Copyright 2006 ARM Limited. All rights reserved
Introduction
ARM DDI 0389B
Functional operation on page SMC functional operation on page
Functional Overview
Functional description on page
Chapter
AHB interface AHB to APB bridge Clock domains on page
Low-power interface on page
2.1 Functional description
2.1.1 AHB interface
2.1.3 Clock domains
smcmreset0n
2.1.4 Low-power interface
AHB clock domain
Memory manager on page Memory interface on page Pad interface on page
2.2 SMC
SMC interface on page APB slave interface on page
Figure 2-3 SMC block diagram
2.2.3 Format
2.2.1 SMC interface
2.2.2 APB slave interface
2.2.4 Memory manager
2.2.6 Pad interface
2.2.7 Interrupts
AHB response signals on page Locked transfers on page
Clock domain operation on page Low-power interface operation on page
Broken bursts on page Bufferable bit of the HPROT signal on page
Removal of AHB error response logic on page
Undefined length INCR bursts
Bufferable bit of the HPROT signal
Broken bursts
Read after write hazard detection buffer
AHB response signals
Locked transfers
Big-endian 32-bit mode
Removal of AHB error response logic
Registered HWDATA
2.3.2 AHB to APB bridge operation
2.3.3 Clock domain operation
Figure 2-6 AHBC memory map
Static memory clocking options
2.3.4 Low-power interface operation
a request input domaincsyreq an acknowledge output domaincsysack
an active output domaincactive
Figure 2-9 Accepting requests
Reset
Operating states Clocking and resets on page
Miscellaneous signals on page APB slave interface operation on page
Power is applied to the device, and hresetn is held LOW
Ready to Low-power
Ready to Reset
Reset to Ready
Low-power to Ready
Memory clock domain
Resets
AHB domain
Synchronous clocking
smcuserstatus70
2.4.3 Miscellaneous signals
smcuserconfig70
smcagtm0sync
smcrstbypass
Hazard handling SRAM memory accesses on page
smcmsync0
smcuseebi
Standard SRAM access Memory address shifting Memory burst alignment
SRAM memory accesses
Memory burst length on page Booting using the SRAM on page
Booting using the SRAM
Memory burst length
Low-power operation
Low-power operation Chip configuration registers
Direct commands on page
Chip configuration registers
PHPFBFIJ VHWF\FOHV VHWRSPRGH
Figure 2-11 Chip configuration registers
DSEBLI
FKLSF\FOHV FKLSRSPRGH
Device pin mechanism
Direct commands
Software mechanism
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Figure 2-12 Device pin mechanism
Functional Overview
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Copyright 2006 ARM Limited. All rights reserved
Figure 2-13 Software mechanism
Functional Overview
ARM DDI 0389B
2.4.7 Interrupts operation
They are divided into SRAM timing tables and diagrams
SRAM timing tables and diagrams
2.4.8 Memory interface operation
Asynchronous write in multiplexed-mode on page
Asynchronous read Asynchronous read in multiplexed-mode on page
Asynchronous write on page
Asynchronous page mode read on page Synchronous burst read on page
Asynchronous read in multiplexed-mode
Figure 2-14 Asynchronous read
Figure 2-15 Asynchronous read in multiplexed-mode
smcdataout0310 output bus. Read data is accepted on the smcdatain0310
Figure 2-17 Asynchronous write in multiplexed-mode
Table 2-10 Page read opmode chip register settings
Asynchronous write in multiplexed-mode
Asynchronous page mode read
Multiplexed-mode page accesses are not supported
Figure 2-19 Synchronous burst read
Figure 2-20 Synchronous burst read in multiplexed-mode
Synchronous burst write
Table 2-16 Synchronous burst write opmode chip register settings
Table 2-17 Synchronous burst write SRAM cycles register settings
Figure 2-21 Synchronous burst write
Figure 2-22 Synchronous burst write in multiplexed-mode
Reads followed by writes Writes followed by reads
For tRC
For tWC
ARM DDI 0389B
Functional Overview
Copyright 2006 ARM Limited. All rights reserved
2-40
Register descriptions on page
Programmer’s Model
About the programmer’s model on page Register summary on page
Chapter
SMC user configuration registers
SMC configuration registers
SMC chip select configuration registers
3.1 About the programmer’s model
Figure 3-3 SMC chip configuration register map
3.2 Register summary
Figure 3-2 SMC configuration register map
Programmer’s Model
Name
Figure 3-4 SMC user configuration register map
Reset value
Base offset
Name
Reset value
Table 3-1 Register summary continued
Base offset
3.3 Register descriptions
3.3.1 SMC Memory Controller Status Register at
Table 3-3 smcmemifcfg Register bit assignments
3.3.2 SMC Memory Interface Configuration Register at
Figure 3-7 smcmemifcfg Register bit assignments
Bits
3.3.3 SMC Set Configuration Register at
Table 3-3 smcmemifcfg Register bit assignments continued
Name
3.3.4 SMC Clear Configuration Register at 0x100C
Bits
Function
3.3.5 SMC Direct Command Register at
3.3.6 SMC Set Cycles Register at
3.3.7 SMC Set Opmode Register at
Figure 3-12 smcsetopmode Register bit assignments
Name
Table 3-8 lists the register bit assignments
Bits
Function
Bits
Configuration Register at 0x1004 on page
Table 3-8 smcsetopmode Register bit assignments continued
Name
3.3.8 SMC Refresh Period 0 Register at
3.3.9 SMC SRAM Cycles Registers 0-3 at 0x1100, 0x1120, 0x1140
3.3.10 SMC Opmode Registers 0-3 at 0x1104, 0x1124, 0x1144
Name
Table 3-11 lists the register bit assignments
Bits
Function
Table 3-11 smcopmode Register bit assignments continued
3.3.11 SMC User Status Register at
Table 3-12 lists the register bit assignments
Bits
Table 3-13 lists the register bit assignments
3.3.12 SMC User Configuration Register at
3.3.13 SMC Peripheral Identification Registers 0-3 at 0x1FE0-0x1FEC
SMC Peripheral Identification Register 2 on page
SMC Peripheral Identification Register
SMC Peripheral Identification Register 1 on page
SMC Peripheral Identification Register 3 on page
SMC Peripheral Identification Register
SMC Peripheral Identification Register
SMC Peripheral Identification Register
Table 3-18 smcperiphid3 Register bit assignments
3.3.14 SMC PrimeCell Identification Registers 0-3 at 0x1FF0-0x1FFC
SMC PrimeCell Identification Register 3 on page
SMC PrimeCell Identification Register
SMC PrimeCell Identification Register 2 on page
SMC PrimeCell Identification Register
The smcpcellid2 Register is hard-coded and the fields within the register indicate the value. Table 3-22 lists the register bit assignments
SMC PrimeCell Identification Register
SMC PrimeCell Identification Register
Chapter
Programmer’s Model for Test
SMC integration test registers on page
Copyright 2006 ARM Limited. All rights reserved
4.1.1 SMC Integration Configuration Register at 0x1E00
4.1 SMC integration test registers
4.1.2
Integration Inputs Register at 0x1E04
Bits
4.1.3 Integration Outputs Register at 0x1E08
Table 4-3 smcintinputs Register bit assignments continued
Name
Chapter
Device Driver Requirements
Memory initialization on page
Copyright 2006 ARM Limited. All rights reserved
5.1 Memory initialization
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Figure 5-1 SMC and memory initialization sheet 1 of
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Figure 5-2 SMC and memory initialization sheet 2 of
Device Driver Requirements
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Figure 5-3 SMC and memory initialization sheet 3 of
Device Driver Requirements
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Copyright 2006 ARM Limited. All rights reserved
Device Driver Requirements
ARM DDI 0389B
AHB signals on page A-4 SMC memory interface signals on page A-5
Signal Descriptions
About the signals list on page A-2 Clocks and resets on page A-3
SMC miscellaneous signals on page A-6 Low-power interface on page A-7
Signal Descriptions
A.1 About the signals list
Figure A-1 AHB MC PL241 grouping of signals
ORFNV
Type
A.2 Clocks and resets
Name
Source
Name
AHB signals
Table A-2 AHB signals
Type
Name
A.4 SMC memory interface signals
Table A-3 SMC memory interface signals
Type
Name
A.5 SMC miscellaneous signals
Table A-4 SMC miscellaneous signals
Type
Type
A.6 Low-power interface
Name
Source
Signal Descriptions
A.7 Configuration signal
Table A-6 Configuration signal
Name
Name
A.8 Scan chains
Table A-7 Scan chain signals
Type
Copyright 2006 ARM Limited. All rights reserved
Signal Descriptions
A-10
ARM DDI 0389B
Glossary
See Advanced Peripheral Bus
See Advanced High-performance Bus
See Advanced Microcontroller Bus Architecture
comprises four beats
See also Beat
incremented
See Should Be Zero
to enable you to access selected parts of the device
See Should Be One
See Should Be Zero or Preserved
has been completed
Copyright 2006 ARM Limited. All rights reserved
Glossary
Glossary-6
ARM DDI 0389B
