SMC Networks PL241, AHB SRAM/NOR specs

Functional Overview

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Figure 2-23 Synchronous read and asynchronous write

Programming tRC and tWC when the controller operates in synchronous mode

For tRC:

•when using memory devices that are not wait-enabled, you must program tRC to be the number of clock cycles required before valid data is available following the assertion of cs_n

•when using memory devices that are wait-enabled, you must program tRC to be the number of clock cycles required before wait is active and stable, following the assertion of cs_n. That is:

t_RC = 3 + t_CEOE

Note

t_CEOE is only required if wait is asserted when oe_n goes LOW.

2-38

Copyright © 2006 ARM Limited. All rights reserved.

ARM DDI 0389B

Image 58

SMC Networks PL241, AHB SRAM/NOR manual TCEOE is only required if wait is asserted when oen goes LOW

Contents

PrimeCell AHB SRAM/NOR Memory Controller PL241 Technical Reference Manual PrimeCell AHB SRAM/NOR Memory Controller PL241Copyright 2006 ARM Limited. All rights reserved Contents Chapter Programmer’s Model for Test List of Tables List of Tables List of Figures Figure A-1 AHB MC PL241 grouping of signals Preface Feedback on Product revision status Using this manualAbout this manual Intended audience Typographical ConventionsBold Timing diagrams Signals Further reading NumberingARM publications Feedback on this product FeedbackFeedback on this manual Introduction This section describes About the AHB MCSMC on AHB interface AHB to APB bridge 3 SMC Low-power interfacesClock domains Supported devices Intel W18 series NOR FLASH, for example 28f128W18td Introduction Copyright 2006 ARM Limited. All rights reserved Functional Overview Functional description This section is divided into AHB clock domain Smcmreset0nLow-power interface Static memory clock domain Format on SMCMain blocks of the SMC are Interrupts on Format SMC interfaceAPB slave interface Memory manager Pad interface Interrupts AHB interface operation Functional operationAHB fixed burst types Undefined length Incr bursts Bufferable bit of the Hprot signalBroken bursts Read after write hazard detection buffer AHB response signalsLocked transfers Registered Hwdata Big-endian 32-bit modeRemoval of AHB error response logic AHB to APB bridge operation Clock domain operation Ahbc memory map 1lists the static memory clocking options Low-power interface operationStatic memory clocking options Static memory clocking options Where Domain is ahb or smc An active output Domaincactive Accepting requests Operating states SMC functional operationSMC states are as follows Clocking and resets Clocking Resets Smcuserstatus70 Miscellaneous signalsSmcuserconfig70 Smcagtm0sync Format block APB slave interface operationHazard handling Sram memory accesses Memory burst length Chip configuration registers Low-power operationMemory manager operation 11 Chip configuration registers Device pin mechanism Direct commandsSoftware mechanism 12 Device pin mechanism 13 Software mechanism Interrupts operation Sram timing tables and diagramsMemory interface operation Asynchronous read opmode chip register settings Asynchronous read Sram cycles register settings 4and -5list the smcopmode00-3 and Sram Register settings 14 Asynchronous read Asynchronous write opmode chip register settings 6and -7list the smcopmode00-3 and Sram Register settingsAsynchronous write Sram cycles register settings 10and -11list the smcopmode00-3 and Sram Register settings 8and -9list the smcopmode00-3 and Sram Register settings10 Page read opmode chip register settings 12 Synchronous burst read opmode chip register settings 12and -13list the smcopmode00-3 and Sram Register settings13 Synchronous burst read Sram cycles register settings 19 Synchronous burst read 14and -15list the smcopmode00-3 and Sram Register settings 20 Synchronous burst read in multiplexed-mode 16 Synchronous burst write opmode chip register settings 16and -17list the smcopmode00-3 and Sram Register settings17 Synchronous burst write Sram cycles register settings 18and -19list the smcopmode00-3 and Sram Register settings 22 Synchronous burst write in multiplexed-mode 20and -21list the smcopmode00-3 and Sram Register settings B0100 B0110 B001 TCEOE is only required if wait is asserted when oen goes LOW TWC = ARM DDI 0389B Programmer’s Model About the programmer’s model 2shows the SMC configuration register map Register summary Name Base offset Type Reset value Description 1lists the SMC Registers Register summary SMC Memory Controller Status Register at Register descriptionsThis section describes the SMC registers 2lists the register bit assignments 3lists the register bit assignments SMC Memory Interface Configuration Register atBits Name Function SMC Set Configuration Register at Smcmemccfgset Register bit assignments 5lists the register bit assignments SMC Clear Configuration Register at 0x100C4lists the register bit assignments Smcmemccfgclr Register bit assignments Bits Name Function 6lists the register bit assignments SMC Direct Command Register atSmcdirectcmd Register bit assignments SMC Set Cycles Register at Lists the register bit assignments SMC Set Opmode Register at 12 smcsetopmode Register bit assignments 8lists the register bit assignments Smcsetopmode Register bit assignments Memory width mw field SMC Sram Cycles Registers 0-3 at 0x1100, 0x1120, 0x1140 SMC Refresh Period 0 Register atSmcrefreshperiod0 Register bit assignments 10lists the register bit assignments SMC Opmode Registers 0-3 at 0x1104, 0x1124, 0x1144 11lists the register bit assignments 11 smcopmode Register bit assignments SMC User Status Register at12lists the register bit assignments 12 smcuserstatus Register bit assignments 13 lists the register bit assignments SMC User Configuration Register at13 smcuserconfig Register bit assignments Bits Name Description SMC Peripheral Identification Register Following section describe the smcperiphid Registers15 smcperiphid0 Register bit assignments Bits Name Function 16 smcperiphid1 Register bit assignments Bits Name Function 17 smcperiphid2 Register bit assignments Bits Name Function SMC PrimeCell Identification Registers 0-3 at 0x1FF0-0x1FFC 19shows the register bit assignments SMC PrimeCell Identification Register These registers cannot be read in the Reset stateFollowing sections describe the smcpcellid Registers 20 smcpcellid0 Register bit assignments Bits Name Function 22 smcpcellid2 Register bit assignments Bits Name Function 23 smcpcellid3 Register bit assignments Bits Name Function Programmer’s Model for Test SMC integration test registers Test registers are provided for integration testingSMC Integration Configuration Register at 0x1E00 Lists the SMC integration test registers Integration Inputs Register at 0x1E04 Smcintinputs Register bit assignments Bits Name Function Integration Outputs Register at 0x1E08 State Device Driver Requirements Memory initialization SMC and memory initialization sheet 1 SMC and memory initialization sheet 2 Where = denotes the appropriate chip select SMC and memory initialization sheet 3 ARM DDI 0389B Signal Descriptions About the signals list Where Ahbc = AHB Configuration signals Table A-1lists the clock and reset signals Clocks and resetsName Type Source Description Destination Where = 0 or C, where C = Configuration AHB signalsTable A-2lists the AHB signals Table A-2 AHB signals SMC memory interface signals Table A-3lists the SMC memory interface signals Table A-4lists the SMC miscellaneous signals SMC miscellaneous signalsTable A-4 SMC miscellaneous signals Low-power interface Table A-5lists the low-power interface signals Table A-6 Configuration signal Configuration signalTable A-6lists the configuration signal Name Source Description Type Destination Table A-7 Scan chain signals Table A-7lists the scan chain signalsScan chains ARM DDI 0389B Advanced High-performance Bus AHB Advanced Microcontroller Bus Architecture Amba See also Little-endian memory Advanced Peripheral Bus APB Data bus IncrementedAn 8-bit data item Multi-master operation That event resource is Unpredictable Divisible by fourSee Unpredictable Other purposes Remapping Has been completedWritten as 0 and read as Reserved Glossary-6