SMC Refresh Period 0 Register at | SMC Networks AHB SRAM/NOR, PL241

Programmer’s Model

3.3.8SMC Refresh Period 0 Register at 0x1020

The read/write smc_refresh_period_0 Register enables the AHB MC to perform refresh cycles for PSRAM devices that you connect to memory interface 0. You cannot access this register in either the Reset or low-power states. Figure 3-13shows the register bit assignments.

8QGHILQHG

SHULRG

			Figure 3-13 smc_refresh_period_0 Register bit assignments
		Table 3-9lists the register bit assignments.
			Table 3-9 smc_refresh_period_0 Register bit assignments
Bits	Name	Function
[31:4]	-	Reserved, read undefined.
[3:0]	period	Sets the number of consecutive memory bursts that are permitted, prior to the AHB MC deasserting
		chip select to enable the PSRAM to initiate a refresh cycle. The options are:
		b0000	= disables the insertion of idle cycles between consecutive bursts
		b0001	= an idle cycle occurs after each burst
		b0010	= an idle cycle occurs after 2 consecutive bursts
		b0011	= an idle cycle occurs after 3 consecutive bursts
		b0100	= an idle cycle occurs after 4 consecutive bursts
		.
		.
		.
		b1111	= an idle cycle occurs after 15 consecutive bursts.

3.3.9SMC SRAM Cycles Registers <0-3> at 0x1100, 0x1120, 0x1140, 0x1160

There is an instance of this register for each SRAM chip supported. The read-only smc_sram_cycles Register cannot be read in the Reset state. Figure 3-14shows the register bit assignments.

8QGHILQHG

WBWU

WBSF

WBZS

WBFHRH

WBZF

WBUF

Figure 3-14 smc_sram_cycles Register bit assignments

ARM DDI 0389B

Copyright © 2006 ARM Limited. All rights reserved.

3-15

Image 75

SMC Networks AHB SRAM/NOR, PL241 SMC Refresh Period 0 Register at, SMC Sram Cycles Registers 0-3 at 0x1100, 0x1120, 0x1140

Contents

PrimeCell AHB SRAM/NOR Memory Controller PL241 PrimeCell AHB SRAM/NOR Memory Controller PL241 Technical Reference ManualCopyright 2006 ARM Limited. All rights reserved Contents Chapter Programmer’s Model for Test List of Tables List of Tables List of Figures Figure A-1 AHB MC PL241 grouping of signals Feedback on Preface Intended audience Using this manualAbout this manual Product revision status Conventions TypographicalBold Signals Timing diagrams Numbering Further readingARM publications Feedback Feedback on this productFeedback on this manual Introduction About the AHB MC This section describesSMC on AHB to APB bridge AHB interface Low-power interfaces 3 SMCClock domains Intel W18 series NOR FLASH, for example 28f128W18td Supported devices Introduction Copyright 2006 ARM Limited. All rights reserved Functional Overview This section is divided into Functional description Static memory clock domain Smcmreset0nLow-power interface AHB clock domain Interrupts on SMCMain blocks of the SMC are Format on Memory manager SMC interfaceAPB slave interface Format Interrupts Pad interface Functional operation AHB interface operationAHB fixed burst types Bufferable bit of the Hprot signal Undefined length Incr burstsBroken bursts AHB response signals Read after write hazard detection bufferLocked transfers AHB to APB bridge operation Big-endian 32-bit modeRemoval of AHB error response logic Registered Hwdata Ahbc memory map Clock domain operation Static memory clocking options Low-power interface operationStatic memory clocking options 1lists the static memory clocking options An active output Domaincactive Where Domain is ahb or smc Accepting requests SMC functional operation Operating statesSMC states are as follows Clocking Clocking and resets Resets Smcagtm0sync Miscellaneous signalsSmcuserconfig70 Smcuserstatus70 APB slave interface operation Format blockHazard handling Sram memory accesses Memory burst length Low-power operation Chip configuration registersMemory manager operation 11 Chip configuration registers Direct commands Device pin mechanismSoftware mechanism 12 Device pin mechanism 13 Software mechanism Sram timing tables and diagrams Interrupts operationMemory interface operation Asynchronous read Sram cycles register settings Asynchronous read opmode chip register settings 14 Asynchronous read 4and -5list the smcopmode00-3 and Sram Register settings 6and -7list the smcopmode00-3 and Sram Register settings Asynchronous write opmode chip register settingsAsynchronous write Sram cycles register settings 8and -9list the smcopmode00-3 and Sram Register settings 10and -11list the smcopmode00-3 and Sram Register settings10 Page read opmode chip register settings 12and -13list the smcopmode00-3 and Sram Register settings 12 Synchronous burst read opmode chip register settings13 Synchronous burst read Sram cycles register settings 19 Synchronous burst read 20 Synchronous burst read in multiplexed-mode 14and -15list the smcopmode00-3 and Sram Register settings 16and -17list the smcopmode00-3 and Sram Register settings 16 Synchronous burst write opmode chip register settings17 Synchronous burst write Sram cycles register settings 22 Synchronous burst write in multiplexed-mode 18and -19list the smcopmode00-3 and Sram Register settings B0100 B0110 B001 20and -21list the smcopmode00-3 and Sram Register settings TCEOE is only required if wait is asserted when oen goes LOW TWC = ARM DDI 0389B Programmer’s Model About the programmer’s model Register summary 2shows the SMC configuration register map 1lists the SMC Registers Name Base offset Type Reset value Description Register summary 2lists the register bit assignments Register descriptionsThis section describes the SMC registers SMC Memory Controller Status Register at SMC Memory Interface Configuration Register at 3lists the register bit assignmentsBits Name Function Smcmemccfgset Register bit assignments SMC Set Configuration Register at Smcmemccfgclr Register bit assignments Bits Name Function SMC Clear Configuration Register at 0x100C4lists the register bit assignments 5lists the register bit assignments SMC Direct Command Register at 6lists the register bit assignmentsSmcdirectcmd Register bit assignments Lists the register bit assignments SMC Set Cycles Register at 12 smcsetopmode Register bit assignments SMC Set Opmode Register at 8lists the register bit assignments Memory width mw field Smcsetopmode Register bit assignments SMC Refresh Period 0 Register at SMC Sram Cycles Registers 0-3 at 0x1100, 0x1120, 0x1140Smcrefreshperiod0 Register bit assignments SMC Opmode Registers 0-3 at 0x1104, 0x1124, 0x1144 10lists the register bit assignments 11lists the register bit assignments 12 smcuserstatus Register bit assignments SMC User Status Register at12lists the register bit assignments 11 smcopmode Register bit assignments Bits Name Description SMC User Configuration Register at13 smcuserconfig Register bit assignments 13 lists the register bit assignments Following section describe the smcperiphid Registers SMC Peripheral Identification Register15 smcperiphid0 Register bit assignments Bits Name Function 17 smcperiphid2 Register bit assignments Bits Name Function 16 smcperiphid1 Register bit assignments Bits Name Function 19shows the register bit assignments SMC PrimeCell Identification Registers 0-3 at 0x1FF0-0x1FFC 20 smcpcellid0 Register bit assignments Bits Name Function These registers cannot be read in the Reset stateFollowing sections describe the smcpcellid Registers SMC PrimeCell Identification Register 23 smcpcellid3 Register bit assignments Bits Name Function 22 smcpcellid2 Register bit assignments Bits Name Function Programmer’s Model for Test Lists the SMC integration test registers Test registers are provided for integration testingSMC Integration Configuration Register at 0x1E00 SMC integration test registers Smcintinputs Register bit assignments Bits Name Function Integration Inputs Register at 0x1E04 State Integration Outputs Register at 0x1E08 Device Driver Requirements Memory initialization SMC and memory initialization sheet 1 SMC and memory initialization sheet 2 SMC and memory initialization sheet 3 Where = denotes the appropriate chip select ARM DDI 0389B Signal Descriptions Where Ahbc = AHB Configuration signals About the signals list Clocks and resets Table A-1lists the clock and reset signalsName Type Source Description Destination Table A-2 AHB signals AHB signalsTable A-2lists the AHB signals Where = 0 or C, where C = Configuration Table A-3lists the SMC memory interface signals SMC memory interface signals SMC miscellaneous signals Table A-4lists the SMC miscellaneous signalsTable A-4 SMC miscellaneous signals Table A-5lists the low-power interface signals Low-power interface Name Source Description Type Destination Configuration signalTable A-6lists the configuration signal Table A-6 Configuration signal Table A-7lists the scan chain signals Table A-7 Scan chain signalsScan chains ARM DDI 0389B Advanced Microcontroller Bus Architecture Amba Advanced High-performance Bus AHB Advanced Peripheral Bus APB See also Little-endian memory Multi-master operation IncrementedAn 8-bit data item Data bus Other purposes Divisible by fourSee Unpredictable That event resource is Unpredictable Reserved Has been completedWritten as 0 and read as Remapping Glossary-6