Manuals
/
SMC Networks
/
Computer Equipment
/
Network Card
SMC Networks
manual PrimeCell AHB SRAM/NOR Memory Controller PL241, Technical Reference Manual
Models:
AHB SRAM/NOR
PL241
1
1
110
110
Download
110 pages
44.4 Kb
1
2
3
4
5
6
7
8
<
>
Specs
Typographical Timing diagrams on page
smcuserconfig70
smcmreset0n
Direct commands on page
Removal of AHB error response logic on page
Signal Descriptions
10 Page read opmode chip register settings
Clock domains on page Low-power interfaces on page
to enable you to access selected parts of the device
Page 1
Image 1
PrimeCell
®
AHB SRAM/NOR Memory Controller (PL241)
Revision: r0p1
Technical Reference Manual
Copyright © 2006 ARM Limited. All rights reserved.
ARM DDI 0389B
Page 2
Page 1
Image 1
Page 2
Contents
Technical Reference Manual
PrimeCell AHB SRAM/NOR Memory Controller PL241
Revision r0p1
Technical Reference Manual
PrimeCell AHB SRAM/NOR Memory Controller PL241
Release Information
Proprietary Notice
Preface
Contents
Chapter
Introduction
Programmer’s Model for Test
Signal Descriptions
Device Driver Requirements
Appendix A
List of Tables
Register summary
List of Figures
Synchronous burst read in multiplexed-mode
About this manual on page
Preface
Feedback on page
Copyright 2006 ARM Limited. All rights reserved
About this manual
Using this manual
Product revision status
where
Typographical Timing diagrams on page
Appendix A Signal Descriptions
Conventions
Typographical
Signals
Timing diagrams
Signal level
Denotes global Advanced eXtensible Interface AXI signals
Denotes Advanced Peripheral Bus APB signals
Denotes Advanced High-performance Bus AHB signals
AMBA 3 APB Protocol v1.0 Specification ARM IHI
Prefix B
Feedback on this product
Feedback
Feedback on this manual
Introduction
Chapter
About the AHB MC on page Supported devices on page
Copyright 2006 ARM Limited. All rights reserved
1.1 About the AHB MC
Clock domains on page Low-power interfaces on page
AHB interface on page AHB to APB bridge on page
1.1.2 AHB to APB bridge
1.1.1 AHB interface
1.1.5 Low-power interfaces
Pseudo Static Random Access Memory PSRAM
1.1.3 SMC
1.1.4 Clock domains
Intel W18 series NOR FLASH, for example 28f128W18td
1.2 Supported devices
Cellular RAM 1.0, 64MB PSRAM, for example mt45w4mw16bfb7011us
Copyright 2006 ARM Limited. All rights reserved
Introduction
ARM DDI 0389B
Functional description on page
Functional Overview
Functional operation on page SMC functional operation on page
Chapter
2.1 Functional description
Low-power interface on page
AHB interface AHB to APB bridge Clock domains on page
2.1.1 AHB interface
2.1.4 Low-power interface
smcmreset0n
2.1.3 Clock domains
AHB clock domain
SMC interface on page APB slave interface on page
2.2 SMC
Memory manager on page Memory interface on page Pad interface on page
Figure 2-3 SMC block diagram
2.2.2 APB slave interface
2.2.1 SMC interface
2.2.3 Format
2.2.4 Memory manager
2.2.7 Interrupts
2.2.6 Pad interface
Broken bursts on page Bufferable bit of the HPROT signal on page
Clock domain operation on page Low-power interface operation on page
AHB response signals on page Locked transfers on page
Removal of AHB error response logic on page
Undefined length INCR bursts
Bufferable bit of the HPROT signal
Broken bursts
Read after write hazard detection buffer
AHB response signals
Locked transfers
Registered HWDATA
Removal of AHB error response logic
Big-endian 32-bit mode
2.3.2 AHB to APB bridge operation
Figure 2-6 AHBC memory map
2.3.3 Clock domain operation
Static memory clocking options
2.3.4 Low-power interface operation
a request input domaincsyreq an acknowledge output domaincsysack
an active output domaincactive
Figure 2-9 Accepting requests
Miscellaneous signals on page APB slave interface operation on page
Operating states Clocking and resets on page
Reset
Power is applied to the device, and hresetn is held LOW
Reset to Ready
Ready to Reset
Ready to Low-power
Low-power to Ready
AHB domain
Resets
Memory clock domain
Synchronous clocking
smcuserconfig70
2.4.3 Miscellaneous signals
smcuserstatus70
smcagtm0sync
smcmsync0
Hazard handling SRAM memory accesses on page
smcrstbypass
smcuseebi
Standard SRAM access Memory address shifting Memory burst alignment
SRAM memory accesses
Memory burst length on page Booting using the SRAM on page
Memory burst length
Booting using the SRAM
Direct commands on page
Low-power operation Chip configuration registers
Low-power operation
Chip configuration registers
DSEBLI
Figure 2-11 Chip configuration registers
PHPFBFIJ VHWF\FOHV VHWRSPRGH
FKLSF\FOHV FKLSRSPRGH
Device pin mechanism
Direct commands
Software mechanism
Functional Overview
Figure 2-12 Device pin mechanism
6WDUW ULWHWLPLQJSDUDPHWHUV DQGRSHUDWLQJPRGHWR
WKHPHPRU\FRQWUROOHU KROGLQJUHJLVWHUV ULWHUHTXLUHGHWHUQDOFKLS
Functional Overview
Figure 2-13 Software mechanism
Copyright 2006 ARM Limited. All rights reserved
ARM DDI 0389B
SRAM timing tables and diagrams
They are divided into SRAM timing tables and diagrams
2.4.7 Interrupts operation
2.4.8 Memory interface operation
Asynchronous write on page
Asynchronous read Asynchronous read in multiplexed-mode on page
Asynchronous write in multiplexed-mode on page
Asynchronous page mode read on page Synchronous burst read on page
Asynchronous read in multiplexed-mode
Figure 2-14 Asynchronous read
Figure 2-15 Asynchronous read in multiplexed-mode
smcdataout0310 output bus. Read data is accepted on the smcdatain0310
Asynchronous write in multiplexed-mode
Table 2-10 Page read opmode chip register settings
Figure 2-17 Asynchronous write in multiplexed-mode
Asynchronous page mode read
Multiplexed-mode page accesses are not supported
Figure 2-19 Synchronous burst read
Figure 2-20 Synchronous burst read in multiplexed-mode
Table 2-17 Synchronous burst write SRAM cycles register settings
Table 2-16 Synchronous burst write opmode chip register settings
Synchronous burst write
Figure 2-21 Synchronous burst write
Figure 2-22 Synchronous burst write in multiplexed-mode
Reads followed by writes Writes followed by reads
For tRC
For tWC
Copyright 2006 ARM Limited. All rights reserved
Functional Overview
ARM DDI 0389B
2-40
About the programmer’s model on page Register summary on page
Programmer’s Model
Register descriptions on page
Chapter
SMC chip select configuration registers
SMC configuration registers
SMC user configuration registers
3.1 About the programmer’s model
Figure 3-2 SMC configuration register map
3.2 Register summary
Figure 3-3 SMC chip configuration register map
Programmer’s Model
Reset value
Figure 3-4 SMC user configuration register map
Name
Base offset
Table 3-1 Register summary continued
Reset value
Name
Base offset
3.3.1 SMC Memory Controller Status Register at
3.3 Register descriptions
Figure 3-7 smcmemifcfg Register bit assignments
3.3.2 SMC Memory Interface Configuration Register at
Table 3-3 smcmemifcfg Register bit assignments
Bits
Table 3-3 smcmemifcfg Register bit assignments continued
3.3.3 SMC Set Configuration Register at
Bits
3.3.4 SMC Clear Configuration Register at 0x100C
Name
Function
3.3.5 SMC Direct Command Register at
3.3.6 SMC Set Cycles Register at
Figure 3-12 smcsetopmode Register bit assignments
3.3.7 SMC Set Opmode Register at
Bits
Table 3-8 lists the register bit assignments
Name
Function
Table 3-8 smcsetopmode Register bit assignments continued
Configuration Register at 0x1004 on page
Bits
Name
3.3.9 SMC SRAM Cycles Registers 0-3 at 0x1100, 0x1120, 0x1140
3.3.8 SMC Refresh Period 0 Register at
3.3.10 SMC Opmode Registers 0-3 at 0x1104, 0x1124, 0x1144
Bits
Table 3-11 lists the register bit assignments
Name
Function
Table 3-12 lists the register bit assignments
3.3.11 SMC User Status Register at
Table 3-11 smcopmode Register bit assignments continued
Bits
Table 3-13 lists the register bit assignments
3.3.12 SMC User Configuration Register at
3.3.13 SMC Peripheral Identification Registers 0-3 at 0x1FE0-0x1FEC
SMC Peripheral Identification Register 1 on page
SMC Peripheral Identification Register
SMC Peripheral Identification Register 2 on page
SMC Peripheral Identification Register 3 on page
SMC Peripheral Identification Register
SMC Peripheral Identification Register
SMC Peripheral Identification Register
Table 3-18 smcperiphid3 Register bit assignments
3.3.14 SMC PrimeCell Identification Registers 0-3 at 0x1FF0-0x1FFC
SMC PrimeCell Identification Register 2 on page
SMC PrimeCell Identification Register
SMC PrimeCell Identification Register 3 on page
SMC PrimeCell Identification Register
The smcpcellid2 Register is hard-coded and the fields within the register indicate the value. Table 3-22 lists the register bit assignments
SMC PrimeCell Identification Register
SMC PrimeCell Identification Register
SMC integration test registers on page
Programmer’s Model for Test
Chapter
Copyright 2006 ARM Limited. All rights reserved
4.1 SMC integration test registers
4.1.1 SMC Integration Configuration Register at 0x1E00
Integration Inputs Register at 0x1E04
4.1.2
Table 4-3 smcintinputs Register bit assignments continued
4.1.3 Integration Outputs Register at 0x1E08
Bits
Name
Memory initialization on page
Device Driver Requirements
Chapter
Copyright 2006 ARM Limited. All rights reserved
5.1 Memory initialization
6WDUW QLWLDOLHYDULDEOHV ULWHWLPLQJLQIRUPDWLRQ WRVPFBVHWBF\FOHV
Figure 5-1 SMC and memory initialization sheet 1 of
KROGLQJ5HJLVWHU ULWHRSHUDWLQJPRGH LQIRUPDWLRQWR VPFBVHWBRSPRGH
KROGLQJ5HJLVWHU
Device Driver Requirements
Figure 5-2 SMC and memory initialization sheet 2 of
6KHHW V PHPRU\GHYLFH 0RGH5HJDFFHVVHGE\
RUDGGUHVV RQO\
Device Driver Requirements
Figure 5-3 SMC and memory initialization sheet 3 of
6KHHW 9HULI\ WKHQHZWLPLQJV DQGRSHUDWLQJ PRGH HV
KHFNIRUFRUUHFW VPFBVUDPBF\FOHVB 5HJLVWHUFRQWHQWV
Copyright 2006 ARM Limited. All rights reserved
Device Driver Requirements
ARM DDI 0389B
About the signals list on page A-2 Clocks and resets on page A-3
Signal Descriptions
AHB signals on page A-4 SMC memory interface signals on page A-5
SMC miscellaneous signals on page A-6 Low-power interface on page A-7
Figure A-1 AHB MC PL241 grouping of signals
A.1 About the signals list
Signal Descriptions
ORFNV
Name
A.2 Clocks and resets
Type
Source
Table A-2 AHB signals
AHB signals
Name
Type
Table A-3 SMC memory interface signals
A.4 SMC memory interface signals
Name
Type
Table A-4 SMC miscellaneous signals
A.5 SMC miscellaneous signals
Name
Type
Name
A.6 Low-power interface
Type
Source
Table A-6 Configuration signal
A.7 Configuration signal
Signal Descriptions
Name
Table A-7 Scan chain signals
A.8 Scan chains
Name
Type
A-10
Signal Descriptions
Copyright 2006 ARM Limited. All rights reserved
ARM DDI 0389B
Glossary
See Advanced Microcontroller Bus Architecture
See Advanced High-performance Bus
See Advanced Peripheral Bus
comprises four beats
incremented
See also Beat
See Should Be One
to enable you to access selected parts of the device
See Should Be Zero
See Should Be Zero or Preserved
has been completed
Glossary-6
Glossary
Copyright 2006 ARM Limited. All rights reserved
ARM DDI 0389B