
Programmer’s Model
3.3.5SMC Direct Command Register at 0x1010
The
This register cannot be written to in either the Reset or
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| 8QGHILQHG |
| $GGU |
VHWBFUH
FPGBW\SH
FKLSBVHOHFW
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| Figure |
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| Table |
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| Table |
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Bits | Name | Function | |
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[31:26] | - | Reserved, undefined. Write as zero. | |
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[25:23] | chip_select | Selects chip configuration register bank to update and enables chip mode register access depending | |
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| on cmd_type. The encoding is: |
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[22:21] | cmd_type | Determines the current command. The encoding is: | |
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| b00 = UpdateRegs and AHB command |
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| b01 = ModeReg access |
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| b10 = UpdateRegs |
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| b11 = ModeReg and UpdateRegs. |
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[20] | set_cre | Maps to configuration register enable, smc_cre, output, when a ModeReg command is issued. The | |
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| encoding is: |
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| b0 = smc_cre is LOW |
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| b1 = smc_cre is HIGH when ModeReg write occurs. |
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[19:0] | addr | Bits mapped to external memory address bits [19:0] when command is ModeReg access. | |
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| Addr[19:16] are undefined. |
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| Addr[15:0] matches wdata[15:0] when the commands are UpdateRegs and AHB command access. |
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Copyright © 2006 ARM Limited. All rights reserved. | ARM DDI 0389B |