SMC Networks PL241, AHB SRAM/NOR manual Register summary

List of Tables

Table 2-21	Synchronous read and asynchronous write opmode chip register settings	2-37
Table 3-1	Register summary	3-4
Table 3-2	smc_memc_status Register bit assignments	3-6
Table 3-3	smc_memif_cfg Register bit assignments	3-7
Table 3-4	smc_memc_cfg_set Register bit assignments	3-9
Table 3-5	smc_memc_cfg_clr Register bit assignments	3-9
Table 3-6	smc_direct_cmd Register bit assignments	3-10
Table 3-7	smc_set_cycles Register bit assignments	3-11
Table 3-8	smc_set_opmode Register bit assignments	3-13
Table 3-9	smc_refresh_period_0 Register bit assignments	3-15
Table 3-10	smc_sram_cycles Register bit assignments	3-16
Table 3-11	smc_opmode Register bit assignments	3-17
Table 3-12	smc_user_status Register bit assignments	3-18
Table 3-13	smc_user_config Register bit assignments	3-19
Table 3-14	smc_periph_id Register bit assignments	3-19
Table 3-15	smc_periph_id_0 Register bit assignments	3-20
Table 3-16	smc_periph_id_1 Register bit assignments	3-21
Table 3-17	smc_periph_id_2 Register bit assignments	3-21
Table 3-18	smc_periph_id_3 Register bit assignments	3-21
Table 3-19	smc_pcell_id Register bit assignments	3-22
Table 3-20	smc_pcell_id_0 Register bit assignments	3-23
Table 3-21	smc_pcell_id_1 Register bit assignments	3-23
Table 3-22	smc_pcell_id_2 Register bit assignments	3-24
Table 3-23	smc_pcell_id_3 Register bit assignments	3-24
Table 4-1	SMC test register summary	4-2
Table 4-2	smc_int_cfg Register bit assignments	4-3
Table 4-3	smc_int_inputs Register bit assignments	4-3
Table 4-4	smc_int_outputs Register bit assignments	4-4
Table A-1	Clocks and resets	A-3
Table A-2	AHB signals	A-4
Table A-3	SMC memory interface signals	A-5
Table A-4	SMC miscellaneous signals	A-6
Table A-5	Low-power interface signals	A-7
Table A-6	Configuration signal	A-8
Table A-7	Scan chain signals	A-9

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