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SMC Networks AHB SRAM/NOR smcmsync0, smcrstbypass, smcuseebi, Reference Manual, Format block

Models: AHB SRAM/NOR PL241

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Functional Overview

smc_msync0

When HIGH, indicates smc_mclk0 is synchronous to smc_aclk. Otherwise they are asynchronous. Ensure that smc_msync0 is tied to the same value as smc_async0.

smc_rst_bypass

Use this signal for ATPG testing only. Tie it LOW for normal operation.

smc_use_ebi

When HIGH, indicates that the SMC must operate with a PrimeCell EBI.

See the ARM PrimeCell External Bus Interface (PL220) Technical

Reference Manual.

2.4.4APB slave interface operation

To enable a clean registered interface to the external infrastructure, the APB interface always adds a wait state for all reads and writes by driving pready LOW during the first cycle of the access phase.

In two instances, a delay of more than one wait state can be generated:

•when a direct command is received and there are outstanding commands that prevent a new command being stored in the command FIFO

•when an APB access is received and a previous direct command has not completed.

2.4.5Format block

This section describes:

•Hazard handling

•SRAM memory accesses on page 2-20.

Hazard handling

There are four types of hazard:

•Read After Read (RAR)

•Write After Write (WAW)

•Read After Write (RAW)

•Write After Read (WAR).

The AHB interface deals with RAW hazards. WAR hazards do not occur in the AHB.

ARM DDI 0389B

Copyright © 2006 ARM Limited. All rights reserved.

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SMC Networks AHB SRAM/NOR smcmsync0, smcrstbypass, smcuseebi, See the ARM PrimeCell External Bus Interface PL220 Technical

Contents

PrimeCell AHB SRAM/NOR Memory Controller PL241 Technical Reference ManualRevision r0p1 Proprietary Notice PrimeCell AHB SRAM/NOR Memory Controller PL241Technical Reference Manual Release InformationIntroduction ContentsPreface ChapterAppendix A Signal DescriptionsProgrammer’s Model for Test Device Driver RequirementsList of Tables Register summary List of Figures Synchronous burst read in multiplexed-mode Copyright 2006 ARM Limited. All rights reserved PrefaceAbout this manual on page Feedback on pagewhere Using this manualAbout this manual Product revision statusTypographical Appendix A Signal DescriptionsTypographical Timing diagrams on page ConventionsDenotes global Advanced eXtensible Interface AXI signals Timing diagramsSignals Signal levelPrefix B Denotes Advanced High-performance Bus AHB signalsDenotes Advanced Peripheral Bus APB signals AMBA 3 APB Protocol v1.0 Specification ARM IHIFeedback Feedback on this productFeedback on this manual Copyright 2006 ARM Limited. All rights reserved ChapterIntroduction About the AHB MC on page Supported devices on pageClock domains on page Low-power interfaces on page 1.1 About the AHB MCAHB interface on page AHB to APB bridge on page 1.1.2 AHB to APB bridge 1.1.1 AHB interface1.1.4 Clock domains Pseudo Static Random Access Memory PSRAM1.1.5 Low-power interfaces 1.1.3 SMC1.2 Supported devices Intel W18 series NOR FLASH, for example 28f128W18tdCellular RAM 1.0, 64MB PSRAM, for example mt45w4mw16bfb7011us Introduction Copyright 2006 ARM Limited. All rights reservedARM DDI 0389B Chapter Functional OverviewFunctional description on page Functional operation on page SMC functional operation on page2.1.1 AHB interface Low-power interface on page2.1 Functional description AHB interface AHB to APB bridge Clock domains on pageAHB clock domain smcmreset0n2.1.4 Low-power interface 2.1.3 Clock domainsFigure 2-3 SMC block diagram 2.2 SMCSMC interface on page APB slave interface on page Memory manager on page Memory interface on page Pad interface on page2.2.4 Memory manager 2.2.1 SMC interface2.2.2 APB slave interface 2.2.3 Format2.2.7 Interrupts 2.2.6 Pad interfaceRemoval of AHB error response logic on page Clock domain operation on page Low-power interface operation on pageBroken bursts on page Bufferable bit of the HPROT signal on page AHB response signals on page Locked transfers on pageBufferable bit of the HPROT signal Undefined length INCR burstsBroken bursts AHB response signals Read after write hazard detection bufferLocked transfers 2.3.2 AHB to APB bridge operation Removal of AHB error response logicRegistered HWDATA Big-endian 32-bit modeFigure 2-6 AHBC memory map 2.3.3 Clock domain operation2.3.4 Low-power interface operation Static memory clocking optionsa request input domaincsyreq an acknowledge output domaincsysack an active output domaincactive Figure 2-9 Accepting requests Power is applied to the device, and hresetn is held LOW Operating states Clocking and resets on pageMiscellaneous signals on page APB slave interface operation on page ResetLow-power to Ready Ready to ResetReset to Ready Ready to Low-powerSynchronous clocking ResetsAHB domain Memory clock domainsmcagtm0sync 2.4.3 Miscellaneous signalssmcuserconfig70 smcuserstatus70smcuseebi Hazard handling SRAM memory accesses on pagesmcmsync0 smcrstbypassSRAM memory accesses Standard SRAM access Memory address shifting Memory burst alignmentMemory burst length on page Booting using the SRAM on page Memory burst length Booting using the SRAMChip configuration registers Low-power operation Chip configuration registersDirect commands on page Low-power operationFKLSF\FOHV FKLSRSPRGH Figure 2-11 Chip configuration registersDSEBLI PHPFBFIJ VHWF\FOHV VHWRSPRGHDirect commands Device pin mechanismSoftware mechanism WKHPHPRU\FRQWUROOHU KROGLQJUHJLVWHUV ULWHUHTXLUHGHWHUQDOFKLS Figure 2-12 Device pin mechanismFunctional Overview 6WDUW ULWHWLPLQJSDUDPHWHUV DQGRSHUDWLQJPRGHWRARM DDI 0389B Figure 2-13 Software mechanismFunctional Overview Copyright 2006 ARM Limited. All rights reserved2.4.8 Memory interface operation They are divided into SRAM timing tables and diagramsSRAM timing tables and diagrams 2.4.7 Interrupts operationAsynchronous page mode read on page Synchronous burst read on page Asynchronous read Asynchronous read in multiplexed-mode on pageAsynchronous write on page Asynchronous write in multiplexed-mode on pageFigure 2-14 Asynchronous read Asynchronous read in multiplexed-modeFigure 2-15 Asynchronous read in multiplexed-mode smcdataout0310 output bus. Read data is accepted on the smcdatain0310 Asynchronous page mode read Table 2-10 Page read opmode chip register settingsAsynchronous write in multiplexed-mode Figure 2-17 Asynchronous write in multiplexed-modeMultiplexed-mode page accesses are not supported Figure 2-19 Synchronous burst read Figure 2-20 Synchronous burst read in multiplexed-mode Figure 2-21 Synchronous burst write Table 2-16 Synchronous burst write opmode chip register settingsTable 2-17 Synchronous burst write SRAM cycles register settings Synchronous burst writeFigure 2-22 Synchronous burst write in multiplexed-mode Reads followed by writes Writes followed by reads For tRC For tWC 2-40 Functional OverviewCopyright 2006 ARM Limited. All rights reserved ARM DDI 0389BChapter Programmer’s ModelAbout the programmer’s model on page Register summary on page Register descriptions on page3.1 About the programmer’s model SMC configuration registersSMC chip select configuration registers SMC user configuration registersProgrammer’s Model 3.2 Register summaryFigure 3-2 SMC configuration register map Figure 3-3 SMC chip configuration register mapBase offset Figure 3-4 SMC user configuration register mapReset value NameBase offset Reset valueTable 3-1 Register summary continued Name3.3.1 SMC Memory Controller Status Register at 3.3 Register descriptionsBits 3.3.2 SMC Memory Interface Configuration Register atFigure 3-7 smcmemifcfg Register bit assignments Table 3-3 smcmemifcfg Register bit assignmentsTable 3-3 smcmemifcfg Register bit assignments continued 3.3.3 SMC Set Configuration Register atFunction 3.3.4 SMC Clear Configuration Register at 0x100CBits Name3.3.5 SMC Direct Command Register at 3.3.6 SMC Set Cycles Register at Figure 3-12 smcsetopmode Register bit assignments 3.3.7 SMC Set Opmode Register atFunction Table 3-8 lists the register bit assignmentsBits NameName Configuration Register at 0x1004 on pageTable 3-8 smcsetopmode Register bit assignments continued Bits3.3.9 SMC SRAM Cycles Registers 0-3 at 0x1100, 0x1120, 0x1140 3.3.8 SMC Refresh Period 0 Register at3.3.10 SMC Opmode Registers 0-3 at 0x1104, 0x1124, 0x1144 Function Table 3-11 lists the register bit assignmentsBits NameBits 3.3.11 SMC User Status Register atTable 3-12 lists the register bit assignments Table 3-11 smcopmode Register bit assignments continued3.3.12 SMC User Configuration Register at Table 3-13 lists the register bit assignments3.3.13 SMC Peripheral Identification Registers 0-3 at 0x1FE0-0x1FEC SMC Peripheral Identification Register 3 on page SMC Peripheral Identification RegisterSMC Peripheral Identification Register 1 on page SMC Peripheral Identification Register 2 on pageTable 3-18 smcperiphid3 Register bit assignments SMC Peripheral Identification RegisterSMC Peripheral Identification Register SMC Peripheral Identification Register3.3.14 SMC PrimeCell Identification Registers 0-3 at 0x1FF0-0x1FFC SMC PrimeCell Identification Register SMC PrimeCell Identification RegisterSMC PrimeCell Identification Register 2 on page SMC PrimeCell Identification Register 3 on pageSMC PrimeCell Identification Register The smcpcellid2 Register is hard-coded and the fields within the register indicate the value. Table 3-22 lists the register bit assignmentsSMC PrimeCell Identification Register Copyright 2006 ARM Limited. All rights reserved Programmer’s Model for TestSMC integration test registers on page Chapter4.1 SMC integration test registers 4.1.1 SMC Integration Configuration Register at 0x1E00Integration Inputs Register at 0x1E04 4.1.2Name 4.1.3 Integration Outputs Register at 0x1E08Table 4-3 smcintinputs Register bit assignments continued BitsCopyright 2006 ARM Limited. All rights reserved Device Driver RequirementsMemory initialization on page Chapter5.1 Memory initialization KROGLQJ5HJLVWHU Figure 5-1 SMC and memory initialization sheet 1 of6WDUW QLWLDOLHYDULDEOHV ULWHWLPLQJLQIRUPDWLRQ WRVPFBVHWBF\FOHV KROGLQJ5HJLVWHU ULWHRSHUDWLQJPRGH LQIRUPDWLRQWR VPFBVHWBRSPRGHRUDGGUHVV RQO\ Figure 5-2 SMC and memory initialization sheet 2 ofDevice Driver Requirements 6KHHW V PHPRU\GHYLFH 0RGH5HJDFFHVVHGE\KHFNIRUFRUUHFW VPFBVUDPBF\FOHVB 5HJLVWHUFRQWHQWV Figure 5-3 SMC and memory initialization sheet 3 ofDevice Driver Requirements 6KHHW 9HULI\ WKHQHZWLPLQJV DQGRSHUDWLQJ PRGH HVDevice Driver Requirements Copyright 2006 ARM Limited. All rights reservedARM DDI 0389B SMC miscellaneous signals on page A-6 Low-power interface on page A-7 Signal DescriptionsAbout the signals list on page A-2 Clocks and resets on page A-3 AHB signals on page A-4 SMC memory interface signals on page A-5ORFNV A.1 About the signals listFigure A-1 AHB MC PL241 grouping of signals Signal DescriptionsSource A.2 Clocks and resetsName TypeType AHB signalsTable A-2 AHB signals NameType A.4 SMC memory interface signalsTable A-3 SMC memory interface signals NameType A.5 SMC miscellaneous signalsTable A-4 SMC miscellaneous signals NameSource A.6 Low-power interfaceName TypeName A.7 Configuration signalTable A-6 Configuration signal Signal DescriptionsType A.8 Scan chainsTable A-7 Scan chain signals NameARM DDI 0389B Signal DescriptionsA-10 Copyright 2006 ARM Limited. All rights reservedGlossary comprises four beats See Advanced High-performance BusSee Advanced Microcontroller Bus Architecture See Advanced Peripheral Busincremented See also BeatSee Should Be Zero or Preserved to enable you to access selected parts of the deviceSee Should Be One See Should Be Zerohas been completed ARM DDI 0389B GlossaryGlossary-6 Copyright 2006 ARM Limited. All rights reserved