Twc = | SMC Networks AHB SRAM/NOR, PL241 guide

Functional Overview

For tWC:

•when using memory devices that are not wait-enabled, you must program tWC to be the number of clock cycles required before the first data is written, following the assertion of cs_n

•when using memory devices that are wait-enabled, you must program tWC to be the number of clock cycles required before wait is active and stable, following the assertion of cs_n. That is:

t_WC = 3

Note

If a memory device is configured so that there are two or less clock cycles between the assertion of wait and data being required then you must program tWC as if the memory device is not wait-enabled.

ARM DDI 0389B

Copyright © 2006 ARM Limited. All rights reserved.

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Image 59

SMC Networks AHB SRAM/NOR, PL241 manual Twc =

Contents

PrimeCell AHB SRAM/NOR Memory Controller PL241 Copyright 2006 ARM Limited. All rights reserved PrimeCell AHB SRAM/NOR Memory Controller PL241Technical Reference Manual Contents Chapter Programmer’s Model for Test List of Tables List of Tables List of Figures Figure A-1 AHB MC PL241 grouping of signals Feedback on Preface Intended audience Using this manualAbout this manual Product revision status Bold ConventionsTypographical Signals Timing diagrams ARM publications NumberingFurther reading Feedback on this manual FeedbackFeedback on this product Introduction SMC on About the AHB MCThis section describes AHB to APB bridge AHB interface Clock domains Low-power interfaces3 SMC Intel W18 series NOR FLASH, for example 28f128W18td Supported devices Introduction Copyright 2006 ARM Limited. All rights reserved Functional Overview This section is divided into Functional description Static memory clock domain Smcmreset0nLow-power interface AHB clock domain Interrupts on SMCMain blocks of the SMC are Format on Memory manager SMC interfaceAPB slave interface Format Interrupts Pad interface AHB fixed burst types Functional operationAHB interface operation Broken bursts Bufferable bit of the Hprot signalUndefined length Incr bursts Locked transfers AHB response signalsRead after write hazard detection buffer AHB to APB bridge operation Big-endian 32-bit modeRemoval of AHB error response logic Registered Hwdata Ahbc memory map Clock domain operation Static memory clocking options Low-power interface operationStatic memory clocking options 1lists the static memory clocking options An active output Domaincactive Where Domain is ahb or smc Accepting requests SMC states are as follows SMC functional operationOperating states Clocking Clocking and resets Resets Smcagtm0sync Miscellaneous signalsSmcuserconfig70 Smcuserstatus70 Hazard handling APB slave interface operationFormat block Sram memory accesses Memory burst length Memory manager operation Low-power operationChip configuration registers 11 Chip configuration registers Software mechanism Direct commandsDevice pin mechanism 12 Device pin mechanism 13 Software mechanism Memory interface operation Sram timing tables and diagramsInterrupts operation Asynchronous read Sram cycles register settings Asynchronous read opmode chip register settings 14 Asynchronous read 4and -5list the smcopmode00-3 and Sram Register settings Asynchronous write Sram cycles register settings 6and -7list the smcopmode00-3 and Sram Register settingsAsynchronous write opmode chip register settings 10 Page read opmode chip register settings 8and -9list the smcopmode00-3 and Sram Register settings10and -11list the smcopmode00-3 and Sram Register settings 13 Synchronous burst read Sram cycles register settings 12and -13list the smcopmode00-3 and Sram Register settings12 Synchronous burst read opmode chip register settings 19 Synchronous burst read 20 Synchronous burst read in multiplexed-mode 14and -15list the smcopmode00-3 and Sram Register settings 17 Synchronous burst write Sram cycles register settings 16and -17list the smcopmode00-3 and Sram Register settings16 Synchronous burst write opmode chip register settings 22 Synchronous burst write in multiplexed-mode 18and -19list the smcopmode00-3 and Sram Register settings B0100 B0110 B001 20and -21list the smcopmode00-3 and Sram Register settings TCEOE is only required if wait is asserted when oen goes LOW TWC = ARM DDI 0389B Programmer’s Model About the programmer’s model Register summary 2shows the SMC configuration register map 1lists the SMC Registers Name Base offset Type Reset value Description Register summary 2lists the register bit assignments Register descriptionsThis section describes the SMC registers SMC Memory Controller Status Register at Bits Name Function SMC Memory Interface Configuration Register at3lists the register bit assignments Smcmemccfgset Register bit assignments SMC Set Configuration Register at Smcmemccfgclr Register bit assignments Bits Name Function SMC Clear Configuration Register at 0x100C4lists the register bit assignments 5lists the register bit assignments Smcdirectcmd Register bit assignments SMC Direct Command Register at6lists the register bit assignments Lists the register bit assignments SMC Set Cycles Register at 12 smcsetopmode Register bit assignments SMC Set Opmode Register at 8lists the register bit assignments Memory width mw field Smcsetopmode Register bit assignments Smcrefreshperiod0 Register bit assignments SMC Refresh Period 0 Register atSMC Sram Cycles Registers 0-3 at 0x1100, 0x1120, 0x1140 SMC Opmode Registers 0-3 at 0x1104, 0x1124, 0x1144 10lists the register bit assignments 11lists the register bit assignments 12 smcuserstatus Register bit assignments SMC User Status Register at12lists the register bit assignments 11 smcopmode Register bit assignments Bits Name Description SMC User Configuration Register at13 smcuserconfig Register bit assignments 13 lists the register bit assignments 15 smcperiphid0 Register bit assignments Bits Name Function Following section describe the smcperiphid RegistersSMC Peripheral Identification Register 17 smcperiphid2 Register bit assignments Bits Name Function 16 smcperiphid1 Register bit assignments Bits Name Function 19shows the register bit assignments SMC PrimeCell Identification Registers 0-3 at 0x1FF0-0x1FFC 20 smcpcellid0 Register bit assignments Bits Name Function These registers cannot be read in the Reset stateFollowing sections describe the smcpcellid Registers SMC PrimeCell Identification Register 23 smcpcellid3 Register bit assignments Bits Name Function 22 smcpcellid2 Register bit assignments Bits Name Function Programmer’s Model for Test Lists the SMC integration test registers Test registers are provided for integration testingSMC Integration Configuration Register at 0x1E00 SMC integration test registers Smcintinputs Register bit assignments Bits Name Function Integration Inputs Register at 0x1E04 State Integration Outputs Register at 0x1E08 Device Driver Requirements Memory initialization SMC and memory initialization sheet 1 SMC and memory initialization sheet 2 SMC and memory initialization sheet 3 Where = denotes the appropriate chip select ARM DDI 0389B Signal Descriptions Where Ahbc = AHB Configuration signals About the signals list Name Type Source Description Destination Clocks and resetsTable A-1lists the clock and reset signals Table A-2 AHB signals AHB signalsTable A-2lists the AHB signals Where = 0 or C, where C = Configuration Table A-3lists the SMC memory interface signals SMC memory interface signals Table A-4 SMC miscellaneous signals SMC miscellaneous signalsTable A-4lists the SMC miscellaneous signals Table A-5lists the low-power interface signals Low-power interface Name Source Description Type Destination Configuration signalTable A-6lists the configuration signal Table A-6 Configuration signal Scan chains Table A-7lists the scan chain signalsTable A-7 Scan chain signals ARM DDI 0389B Advanced Microcontroller Bus Architecture Amba Advanced High-performance Bus AHB Advanced Peripheral Bus APB See also Little-endian memory Multi-master operation IncrementedAn 8-bit data item Data bus Other purposes Divisible by fourSee Unpredictable That event resource is Unpredictable Reserved Has been completedWritten as 0 and read as Remapping Glossary-6