Clocks and resets | SMC Networks AHB SRAM/NOR, PL241 specification

Signal Descriptions

A.2 Clocks and resets

Table A-1lists the clock and reset signals.

				Table A-1 Clocks and resets

	Name	Type	Source/	Description
	Name	Type	destination	Description
			destination

	hclk	Input	Clock source	AHB clock

	hresetn	Input	Reset source	AHB clock domain reset

	smc_aclk	Input	Clock source	SMC AHB clock

	smc_mclk0	Input	Clock source	SMC memory clock

	smc_mclk0n	Input	Clock source	SMC inverted memory clock

	smc_mreset0n	Input	Reset source	SMC memory clock domain reset

ARM DDI 0389B

Copyright © 2006 ARM Limited. All rights reserved.

A-3

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SMC Networks AHB SRAM/NOR, PL241 manual Clocks and resets, Table A-1lists the clock and reset signals

Contents

PrimeCell AHB SRAM/NOR Memory Controller PL241 Technical Reference Manual PrimeCell AHB SRAM/NOR Memory Controller PL241Copyright 2006 ARM Limited. All rights reserved Contents Chapter Programmer’s Model for Test List of Tables List of Tables List of Figures Figure A-1 AHB MC PL241 grouping of signals Feedback on Preface About this manual Using this manualProduct revision status Intended audience Typographical ConventionsBold Signals Timing diagrams Further reading NumberingARM publications Feedback on this product FeedbackFeedback on this manual Introduction This section describes About the AHB MCSMC on AHB to APB bridge AHB interface 3 SMC Low-power interfacesClock domains Intel W18 series NOR FLASH, for example 28f128W18td Supported devices Introduction Copyright 2006 ARM Limited. All rights reserved Functional Overview This section is divided into Functional description Low-power interface Smcmreset0nAHB clock domain Static memory clock domain Main blocks of the SMC are SMCFormat on Interrupts on APB slave interface SMC interfaceFormat Memory manager Interrupts Pad interface AHB interface operation Functional operationAHB fixed burst types Undefined length Incr bursts Bufferable bit of the Hprot signalBroken bursts Read after write hazard detection buffer AHB response signalsLocked transfers Removal of AHB error response logic Big-endian 32-bit modeRegistered Hwdata AHB to APB bridge operation Ahbc memory map Clock domain operation Static memory clocking options Low-power interface operation1lists the static memory clocking options Static memory clocking options An active output Domaincactive Where Domain is ahb or smc Accepting requests Operating states SMC functional operationSMC states are as follows Clocking Clocking and resets Resets Smcuserconfig70 Miscellaneous signalsSmcuserstatus70 Smcagtm0sync Format block APB slave interface operationHazard handling Sram memory accesses Memory burst length Chip configuration registers Low-power operationMemory manager operation 11 Chip configuration registers Device pin mechanism Direct commandsSoftware mechanism 12 Device pin mechanism 13 Software mechanism Interrupts operation Sram timing tables and diagramsMemory interface operation Asynchronous read Sram cycles register settings Asynchronous read opmode chip register settings 14 Asynchronous read 4and -5list the smcopmode00-3 and Sram Register settings Asynchronous write opmode chip register settings 6and -7list the smcopmode00-3 and Sram Register settingsAsynchronous write Sram cycles register settings 10and -11list the smcopmode00-3 and Sram Register settings 8and -9list the smcopmode00-3 and Sram Register settings10 Page read opmode chip register settings 12 Synchronous burst read opmode chip register settings 12and -13list the smcopmode00-3 and Sram Register settings13 Synchronous burst read Sram cycles register settings 19 Synchronous burst read 20 Synchronous burst read in multiplexed-mode 14and -15list the smcopmode00-3 and Sram Register settings 16 Synchronous burst write opmode chip register settings 16and -17list the smcopmode00-3 and Sram Register settings17 Synchronous burst write Sram cycles register settings 22 Synchronous burst write in multiplexed-mode 18and -19list the smcopmode00-3 and Sram Register settings B0100 B0110 B001 20and -21list the smcopmode00-3 and Sram Register settings TCEOE is only required if wait is asserted when oen goes LOW TWC = ARM DDI 0389B Programmer’s Model About the programmer’s model Register summary 2shows the SMC configuration register map 1lists the SMC Registers Name Base offset Type Reset value Description Register summary This section describes the SMC registers Register descriptionsSMC Memory Controller Status Register at 2lists the register bit assignments 3lists the register bit assignments SMC Memory Interface Configuration Register atBits Name Function Smcmemccfgset Register bit assignments SMC Set Configuration Register at 4lists the register bit assignments SMC Clear Configuration Register at 0x100C5lists the register bit assignments Smcmemccfgclr Register bit assignments Bits Name Function 6lists the register bit assignments SMC Direct Command Register atSmcdirectcmd Register bit assignments Lists the register bit assignments SMC Set Cycles Register at 12 smcsetopmode Register bit assignments SMC Set Opmode Register at 8lists the register bit assignments Memory width mw field Smcsetopmode Register bit assignments SMC Sram Cycles Registers 0-3 at 0x1100, 0x1120, 0x1140 SMC Refresh Period 0 Register atSmcrefreshperiod0 Register bit assignments SMC Opmode Registers 0-3 at 0x1104, 0x1124, 0x1144 10lists the register bit assignments 11lists the register bit assignments 12lists the register bit assignments SMC User Status Register at11 smcopmode Register bit assignments 12 smcuserstatus Register bit assignments 13 smcuserconfig Register bit assignments SMC User Configuration Register at13 lists the register bit assignments Bits Name Description SMC Peripheral Identification Register Following section describe the smcperiphid Registers15 smcperiphid0 Register bit assignments Bits Name Function 17 smcperiphid2 Register bit assignments Bits Name Function 16 smcperiphid1 Register bit assignments Bits Name Function 19shows the register bit assignments SMC PrimeCell Identification Registers 0-3 at 0x1FF0-0x1FFC Following sections describe the smcpcellid Registers These registers cannot be read in the Reset stateSMC PrimeCell Identification Register 20 smcpcellid0 Register bit assignments Bits Name Function 23 smcpcellid3 Register bit assignments Bits Name Function 22 smcpcellid2 Register bit assignments Bits Name Function Programmer’s Model for Test SMC Integration Configuration Register at 0x1E00 Test registers are provided for integration testingSMC integration test registers Lists the SMC integration test registers Smcintinputs Register bit assignments Bits Name Function Integration Inputs Register at 0x1E04 State Integration Outputs Register at 0x1E08 Device Driver Requirements Memory initialization SMC and memory initialization sheet 1 SMC and memory initialization sheet 2 SMC and memory initialization sheet 3 Where = denotes the appropriate chip select ARM DDI 0389B Signal Descriptions Where Ahbc = AHB Configuration signals About the signals list Table A-1lists the clock and reset signals Clocks and resetsName Type Source Description Destination Table A-2lists the AHB signals AHB signalsWhere = 0 or C, where C = Configuration Table A-2 AHB signals Table A-3lists the SMC memory interface signals SMC memory interface signals Table A-4lists the SMC miscellaneous signals SMC miscellaneous signalsTable A-4 SMC miscellaneous signals Table A-5lists the low-power interface signals Low-power interface Table A-6lists the configuration signal Configuration signalTable A-6 Configuration signal Name Source Description Type Destination Table A-7 Scan chain signals Table A-7lists the scan chain signalsScan chains ARM DDI 0389B Advanced Microcontroller Bus Architecture Amba Advanced High-performance Bus AHB Advanced Peripheral Bus APB See also Little-endian memory An 8-bit data item IncrementedData bus Multi-master operation See Unpredictable Divisible by fourThat event resource is Unpredictable Other purposes Written as 0 and read as Has been completedRemapping Reserved Glossary-6