B0100 B0110 B001 | SMC Networks AHB SRAM/NOR, PL241 specification

Functional Overview

Synchronous read and asynchronous write

Table 2-20and Table 2-21list the smc_opmode0_<0-3> and SRAM Register settings.

Table 2-20 Synchronous read and asynchronous write opmode chip register settings

Field	mw	rd_sync	rd_bl	wr_sync	wr_bl	baa	adv	bls	ba

Value	-	b1	b001	b0	b000	b0	b1	b0	-

Table 2-21 Synchronous read and asynchronous write opmode chip register settings

Field	t_rc	t_wc	t_ceoe	t_wp	t_pc	t_tr

Value	b0100	b0110	b010	b001	-	b011

Figure 2-23 on page 2-38shows the turnaround time tTR, enforced between synchronous read and asynchronous write. The turnaround time is enforced between:

•Reads followed by writes

•Writes followed by reads

•Read following a read from a different chip select.

ARM DDI 0389B

Copyright © 2006 ARM Limited. All rights reserved.

2-37

Image 57

SMC Networks AHB SRAM/NOR, PL241 manual 20and -21list the smcopmode00-3 and Sram Register settings, B0100 B0110 B001

Contents

PrimeCell AHB SRAM/NOR Memory Controller PL241 PrimeCell AHB SRAM/NOR Memory Controller PL241 Technical Reference ManualCopyright 2006 ARM Limited. All rights reserved Contents Chapter Programmer’s Model for Test List of Tables List of Tables List of Figures Figure A-1 AHB MC PL241 grouping of signals Feedback on Preface About this manual Using this manualProduct revision status Intended audience Conventions TypographicalBold Signals Timing diagrams Numbering Further readingARM publications Feedback Feedback on this productFeedback on this manual Introduction About the AHB MC This section describesSMC on AHB to APB bridge AHB interface Low-power interfaces 3 SMCClock domains Intel W18 series NOR FLASH, for example 28f128W18td Supported devices Introduction Copyright 2006 ARM Limited. All rights reserved Functional Overview This section is divided into Functional description Low-power interface Smcmreset0nAHB clock domain Static memory clock domain Main blocks of the SMC are SMCFormat on Interrupts on APB slave interface SMC interfaceFormat Memory manager Interrupts Pad interface Functional operation AHB interface operationAHB fixed burst types Bufferable bit of the Hprot signal Undefined length Incr burstsBroken bursts AHB response signals Read after write hazard detection bufferLocked transfers Removal of AHB error response logic Big-endian 32-bit modeRegistered Hwdata AHB to APB bridge operation Ahbc memory map Clock domain operation Static memory clocking options Low-power interface operation1lists the static memory clocking options Static memory clocking options An active output Domaincactive Where Domain is ahb or smc Accepting requests SMC functional operation Operating statesSMC states are as follows Clocking Clocking and resets Resets Smcuserconfig70 Miscellaneous signalsSmcuserstatus70 Smcagtm0sync APB slave interface operation Format blockHazard handling Sram memory accesses Memory burst length Low-power operation Chip configuration registersMemory manager operation 11 Chip configuration registers Direct commands Device pin mechanismSoftware mechanism 12 Device pin mechanism 13 Software mechanism Sram timing tables and diagrams Interrupts operationMemory interface operation Asynchronous read Sram cycles register settings Asynchronous read opmode chip register settings 14 Asynchronous read 4and -5list the smcopmode00-3 and Sram Register settings 6and -7list the smcopmode00-3 and Sram Register settings Asynchronous write opmode chip register settingsAsynchronous write Sram cycles register settings 8and -9list the smcopmode00-3 and Sram Register settings 10and -11list the smcopmode00-3 and Sram Register settings10 Page read opmode chip register settings 12and -13list the smcopmode00-3 and Sram Register settings 12 Synchronous burst read opmode chip register settings13 Synchronous burst read Sram cycles register settings 19 Synchronous burst read 20 Synchronous burst read in multiplexed-mode 14and -15list the smcopmode00-3 and Sram Register settings 16and -17list the smcopmode00-3 and Sram Register settings 16 Synchronous burst write opmode chip register settings17 Synchronous burst write Sram cycles register settings 22 Synchronous burst write in multiplexed-mode 18and -19list the smcopmode00-3 and Sram Register settings B0100 B0110 B001 20and -21list the smcopmode00-3 and Sram Register settings TCEOE is only required if wait is asserted when oen goes LOW TWC = ARM DDI 0389B Programmer’s Model About the programmer’s model Register summary 2shows the SMC configuration register map 1lists the SMC Registers Name Base offset Type Reset value Description Register summary This section describes the SMC registers Register descriptionsSMC Memory Controller Status Register at 2lists the register bit assignments SMC Memory Interface Configuration Register at 3lists the register bit assignmentsBits Name Function Smcmemccfgset Register bit assignments SMC Set Configuration Register at 4lists the register bit assignments SMC Clear Configuration Register at 0x100C5lists the register bit assignments Smcmemccfgclr Register bit assignments Bits Name Function SMC Direct Command Register at 6lists the register bit assignmentsSmcdirectcmd Register bit assignments Lists the register bit assignments SMC Set Cycles Register at 12 smcsetopmode Register bit assignments SMC Set Opmode Register at 8lists the register bit assignments Memory width mw field Smcsetopmode Register bit assignments SMC Refresh Period 0 Register at SMC Sram Cycles Registers 0-3 at 0x1100, 0x1120, 0x1140Smcrefreshperiod0 Register bit assignments SMC Opmode Registers 0-3 at 0x1104, 0x1124, 0x1144 10lists the register bit assignments 11lists the register bit assignments 12lists the register bit assignments SMC User Status Register at11 smcopmode Register bit assignments 12 smcuserstatus Register bit assignments 13 smcuserconfig Register bit assignments SMC User Configuration Register at13 lists the register bit assignments Bits Name Description Following section describe the smcperiphid Registers SMC Peripheral Identification Register15 smcperiphid0 Register bit assignments Bits Name Function 17 smcperiphid2 Register bit assignments Bits Name Function 16 smcperiphid1 Register bit assignments Bits Name Function 19shows the register bit assignments SMC PrimeCell Identification Registers 0-3 at 0x1FF0-0x1FFC Following sections describe the smcpcellid Registers These registers cannot be read in the Reset stateSMC PrimeCell Identification Register 20 smcpcellid0 Register bit assignments Bits Name Function 23 smcpcellid3 Register bit assignments Bits Name Function 22 smcpcellid2 Register bit assignments Bits Name Function Programmer’s Model for Test SMC Integration Configuration Register at 0x1E00 Test registers are provided for integration testingSMC integration test registers Lists the SMC integration test registers Smcintinputs Register bit assignments Bits Name Function Integration Inputs Register at 0x1E04 State Integration Outputs Register at 0x1E08 Device Driver Requirements Memory initialization SMC and memory initialization sheet 1 SMC and memory initialization sheet 2 SMC and memory initialization sheet 3 Where = denotes the appropriate chip select ARM DDI 0389B Signal Descriptions Where Ahbc = AHB Configuration signals About the signals list Clocks and resets Table A-1lists the clock and reset signalsName Type Source Description Destination Table A-2lists the AHB signals AHB signalsWhere = 0 or C, where C = Configuration Table A-2 AHB signals Table A-3lists the SMC memory interface signals SMC memory interface signals SMC miscellaneous signals Table A-4lists the SMC miscellaneous signalsTable A-4 SMC miscellaneous signals Table A-5lists the low-power interface signals Low-power interface Table A-6lists the configuration signal Configuration signalTable A-6 Configuration signal Name Source Description Type Destination Table A-7lists the scan chain signals Table A-7 Scan chain signalsScan chains ARM DDI 0389B Advanced Microcontroller Bus Architecture Amba Advanced High-performance Bus AHB Advanced Peripheral Bus APB See also Little-endian memory An 8-bit data item IncrementedData bus Multi-master operation See Unpredictable Divisible by fourThat event resource is Unpredictable Other purposes Written as 0 and read as Has been completedRemapping Reserved Glossary-6