SMC Networks AHB SRAM/NOR, PL241 manual Clock domains, AHB clock domain, Static memory clock domain

Functional Overview

2.1.3Clock domains

The memory controller has two clock domains:

AHB clock domain

This is clocked by hclk, smc_aclk and reset by hresetn.

Static memory clock domain

This is clocked by smc_mclk0, smc_mclk0n and reset by

smc_mreset0n.

Figure 2-2shows the two clock domains.

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Figure 2-2 AHB MC (PL241) clock domains

The memory controller supports many different options for clocking the different domains.

See Clock domain operation on page 2-11for more information.

2.1.4Low-power interface

The memory controller has two low-power interfaces, one for each clock domain. These operate with a simple three signal protocol. It is expected that a system clock controller drives these interfaces and associated clocks. Each domain has individual control to enable independent handshaking with the system clock controller.

See Low-power interface operation on page 2-12for more information.

ARM DDI 0389B Copyright © 2006 ARM Limited. All rights reserved. 2-3