SMC Networks AHB SRAM/NOR, PL241 manual List of Figures

List of Figures

PrimeCell AHB SRAM/NOR Memory Controller (PL241) Technical Reference Manual

	Key to timing diagram conventions	xii
Figure 1-1	AHB MC (PL241) configuration	1-2
Figure 2-1	AHB MC (PL241) configuration	2-2
Figure 2-2	AHB MC (PL241) clock domains	2-3
Figure 2-3	SMC block diagram	2-4
Figure 2-4	SMC SRAM pad interface external connections	2-6
Figure 2-5	Big-endian implementation	2-10
Figure 2-6	AHBC memory map	2-11
Figure 2-7	Request to enter low-power mode	2-13
Figure 2-8	AHB domain denying a low-power request	2-13
Figure 2-9	Accepting requests	2-14
Figure 2-10	SMC aclk domain FSM	2-15
Figure 2-11	Chip configuration registers	2-23
Figure 2-12	Device pin mechanism	2-25
Figure 2-13	Software mechanism	2-26
Figure 2-14	Asynchronous read	2-29
Figure 2-15	Asynchronous read in multiplexed-mode	2-29
Figure 2-16	Asynchronous write	2-30
Figure 2-17	Asynchronous write in multiplexed-mode	2-31
Figure 2-18	Page read	2-32
Figure 2-19	Synchronous burst read	2-33

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