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PL241 Functional Overview, Copyright 2006 ARM Limited. All rights reserved, 2-40
Models:
AHB SRAM/NOR
PL241
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Specification
Typographical Timing diagrams on page
smcuserconfig70
smcmreset0n
Direct commands on page
Removal of AHB error response logic on page
Signal Descriptions
10 Page read opmode chip register settings
Clock domains on page Low-power interfaces on page
to enable you to access selected parts of the device
Page 60
Image 60
Functional Overview
2-40
Copyright © 2006 ARM Limited. All rights reserved.
ARM DDI 0389B
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Contents
PrimeCell AHB SRAM/NOR Memory Controller PL241
Technical Reference Manual
Revision r0p1
PrimeCell AHB SRAM/NOR Memory Controller PL241
Technical Reference Manual
Release Information
Proprietary Notice
Contents
Preface
Chapter
Introduction
Signal Descriptions
Programmer’s Model for Test
Device Driver Requirements
Appendix A
List of Tables
Register summary
List of Figures
Synchronous burst read in multiplexed-mode
Preface
About this manual on page
Feedback on page
Copyright 2006 ARM Limited. All rights reserved
Using this manual
About this manual
Product revision status
where
Appendix A Signal Descriptions
Typographical Timing diagrams on page
Conventions
Typographical
Timing diagrams
Signals
Signal level
Denotes global Advanced eXtensible Interface AXI signals
Denotes Advanced High-performance Bus AHB signals
Denotes Advanced Peripheral Bus APB signals
AMBA 3 APB Protocol v1.0 Specification ARM IHI
Prefix B
Feedback
Feedback on this product
Feedback on this manual
Chapter
Introduction
About the AHB MC on page Supported devices on page
Copyright 2006 ARM Limited. All rights reserved
Clock domains on page Low-power interfaces on page
1.1 About the AHB MC
AHB interface on page AHB to APB bridge on page
1.1.1 AHB interface
1.1.2 AHB to APB bridge
Pseudo Static Random Access Memory PSRAM
1.1.5 Low-power interfaces
1.1.3 SMC
1.1.4 Clock domains
1.2 Supported devices
Intel W18 series NOR FLASH, for example 28f128W18td
Cellular RAM 1.0, 64MB PSRAM, for example mt45w4mw16bfb7011us
Introduction
Copyright 2006 ARM Limited. All rights reserved
ARM DDI 0389B
Functional Overview
Functional description on page
Functional operation on page SMC functional operation on page
Chapter
Low-power interface on page
2.1 Functional description
AHB interface AHB to APB bridge Clock domains on page
2.1.1 AHB interface
smcmreset0n
2.1.4 Low-power interface
2.1.3 Clock domains
AHB clock domain
2.2 SMC
SMC interface on page APB slave interface on page
Memory manager on page Memory interface on page Pad interface on page
Figure 2-3 SMC block diagram
2.2.1 SMC interface
2.2.2 APB slave interface
2.2.3 Format
2.2.4 Memory manager
2.2.6 Pad interface
2.2.7 Interrupts
Clock domain operation on page Low-power interface operation on page
Broken bursts on page Bufferable bit of the HPROT signal on page
AHB response signals on page Locked transfers on page
Removal of AHB error response logic on page
Bufferable bit of the HPROT signal
Undefined length INCR bursts
Broken bursts
AHB response signals
Read after write hazard detection buffer
Locked transfers
Removal of AHB error response logic
Registered HWDATA
Big-endian 32-bit mode
2.3.2 AHB to APB bridge operation
2.3.3 Clock domain operation
Figure 2-6 AHBC memory map
2.3.4 Low-power interface operation
Static memory clocking options
a request input domaincsyreq an acknowledge output domaincsysack
an active output domaincactive
Figure 2-9 Accepting requests
Operating states Clocking and resets on page
Miscellaneous signals on page APB slave interface operation on page
Reset
Power is applied to the device, and hresetn is held LOW
Ready to Reset
Reset to Ready
Ready to Low-power
Low-power to Ready
Resets
AHB domain
Memory clock domain
Synchronous clocking
2.4.3 Miscellaneous signals
smcuserconfig70
smcuserstatus70
smcagtm0sync
Hazard handling SRAM memory accesses on page
smcmsync0
smcrstbypass
smcuseebi
SRAM memory accesses
Standard SRAM access Memory address shifting Memory burst alignment
Memory burst length on page Booting using the SRAM on page
Booting using the SRAM
Memory burst length
Low-power operation Chip configuration registers
Direct commands on page
Low-power operation
Chip configuration registers
Figure 2-11 Chip configuration registers
DSEBLI
PHPFBFIJ VHWF\FOHV VHWRSPRGH
FKLSF\FOHV FKLSRSPRGH
Direct commands
Device pin mechanism
Software mechanism
Figure 2-12 Device pin mechanism
Functional Overview
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Figure 2-13 Software mechanism
Functional Overview
Copyright 2006 ARM Limited. All rights reserved
ARM DDI 0389B
They are divided into SRAM timing tables and diagrams
SRAM timing tables and diagrams
2.4.7 Interrupts operation
2.4.8 Memory interface operation
Asynchronous read Asynchronous read in multiplexed-mode on page
Asynchronous write on page
Asynchronous write in multiplexed-mode on page
Asynchronous page mode read on page Synchronous burst read on page
Figure 2-14 Asynchronous read
Asynchronous read in multiplexed-mode
Figure 2-15 Asynchronous read in multiplexed-mode
smcdataout0310 output bus. Read data is accepted on the smcdatain0310
Table 2-10 Page read opmode chip register settings
Asynchronous write in multiplexed-mode
Figure 2-17 Asynchronous write in multiplexed-mode
Asynchronous page mode read
Multiplexed-mode page accesses are not supported
Figure 2-19 Synchronous burst read
Figure 2-20 Synchronous burst read in multiplexed-mode
Table 2-16 Synchronous burst write opmode chip register settings
Table 2-17 Synchronous burst write SRAM cycles register settings
Synchronous burst write
Figure 2-21 Synchronous burst write
Figure 2-22 Synchronous burst write in multiplexed-mode
Reads followed by writes Writes followed by reads
For tRC
For tWC
Functional Overview
Copyright 2006 ARM Limited. All rights reserved
ARM DDI 0389B
2-40
Programmer’s Model
About the programmer’s model on page Register summary on page
Register descriptions on page
Chapter
SMC configuration registers
SMC chip select configuration registers
SMC user configuration registers
3.1 About the programmer’s model
3.2 Register summary
Figure 3-2 SMC configuration register map
Figure 3-3 SMC chip configuration register map
Programmer’s Model
Figure 3-4 SMC user configuration register map
Reset value
Name
Base offset
Reset value
Table 3-1 Register summary continued
Name
Base offset
3.3 Register descriptions
3.3.1 SMC Memory Controller Status Register at
3.3.2 SMC Memory Interface Configuration Register at
Figure 3-7 smcmemifcfg Register bit assignments
Table 3-3 smcmemifcfg Register bit assignments
Bits
3.3.3 SMC Set Configuration Register at
Table 3-3 smcmemifcfg Register bit assignments continued
3.3.4 SMC Clear Configuration Register at 0x100C
Bits
Name
Function
3.3.5 SMC Direct Command Register at
3.3.6 SMC Set Cycles Register at
3.3.7 SMC Set Opmode Register at
Figure 3-12 smcsetopmode Register bit assignments
Table 3-8 lists the register bit assignments
Bits
Name
Function
Configuration Register at 0x1004 on page
Table 3-8 smcsetopmode Register bit assignments continued
Bits
Name
3.3.8 SMC Refresh Period 0 Register at
3.3.9 SMC SRAM Cycles Registers 0-3 at 0x1100, 0x1120, 0x1140
3.3.10 SMC Opmode Registers 0-3 at 0x1104, 0x1124, 0x1144
Table 3-11 lists the register bit assignments
Bits
Name
Function
3.3.11 SMC User Status Register at
Table 3-12 lists the register bit assignments
Table 3-11 smcopmode Register bit assignments continued
Bits
3.3.12 SMC User Configuration Register at
Table 3-13 lists the register bit assignments
3.3.13 SMC Peripheral Identification Registers 0-3 at 0x1FE0-0x1FEC
SMC Peripheral Identification Register
SMC Peripheral Identification Register 1 on page
SMC Peripheral Identification Register 2 on page
SMC Peripheral Identification Register 3 on page
SMC Peripheral Identification Register
SMC Peripheral Identification Register
SMC Peripheral Identification Register
Table 3-18 smcperiphid3 Register bit assignments
3.3.14 SMC PrimeCell Identification Registers 0-3 at 0x1FF0-0x1FFC
SMC PrimeCell Identification Register
SMC PrimeCell Identification Register 2 on page
SMC PrimeCell Identification Register 3 on page
SMC PrimeCell Identification Register
SMC PrimeCell Identification Register
The smcpcellid2 Register is hard-coded and the fields within the register indicate the value. Table 3-22 lists the register bit assignments
SMC PrimeCell Identification Register
Programmer’s Model for Test
SMC integration test registers on page
Chapter
Copyright 2006 ARM Limited. All rights reserved
4.1.1 SMC Integration Configuration Register at 0x1E00
4.1 SMC integration test registers
4.1.2
Integration Inputs Register at 0x1E04
4.1.3 Integration Outputs Register at 0x1E08
Table 4-3 smcintinputs Register bit assignments continued
Bits
Name
Device Driver Requirements
Memory initialization on page
Chapter
Copyright 2006 ARM Limited. All rights reserved
5.1 Memory initialization
Figure 5-1 SMC and memory initialization sheet 1 of
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Figure 5-2 SMC and memory initialization sheet 2 of
Device Driver Requirements
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Figure 5-3 SMC and memory initialization sheet 3 of
Device Driver Requirements
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Device Driver Requirements
Copyright 2006 ARM Limited. All rights reserved
ARM DDI 0389B
Signal Descriptions
About the signals list on page A-2 Clocks and resets on page A-3
AHB signals on page A-4 SMC memory interface signals on page A-5
SMC miscellaneous signals on page A-6 Low-power interface on page A-7
A.1 About the signals list
Figure A-1 AHB MC PL241 grouping of signals
Signal Descriptions
ORFNV
A.2 Clocks and resets
Name
Type
Source
AHB signals
Table A-2 AHB signals
Name
Type
A.4 SMC memory interface signals
Table A-3 SMC memory interface signals
Name
Type
A.5 SMC miscellaneous signals
Table A-4 SMC miscellaneous signals
Name
Type
A.6 Low-power interface
Name
Type
Source
A.7 Configuration signal
Table A-6 Configuration signal
Signal Descriptions
Name
A.8 Scan chains
Table A-7 Scan chain signals
Name
Type
Signal Descriptions
A-10
Copyright 2006 ARM Limited. All rights reserved
ARM DDI 0389B
Glossary
See Advanced High-performance Bus
See Advanced Microcontroller Bus Architecture
See Advanced Peripheral Bus
comprises four beats
See also Beat
incremented
to enable you to access selected parts of the device
See Should Be One
See Should Be Zero
See Should Be Zero or Preserved
has been completed
Glossary
Glossary-6
Copyright 2006 ARM Limited. All rights reserved
ARM DDI 0389B