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Signal Descriptions
A.5 SMC miscellaneous signals
Table A-4 lists the SMC miscellaneous signals.
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Name | Type | Source/ | Description | |
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smc_async0 | Input | AHB clock synchronous to memory clock | ||
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smc_msync0 | Input | Memory clock synchronous to AHB clock | ||
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smc_a_gt_m0_sync | Input | When HIGH, indicates that smc_aclk is greater than and | ||
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| synchronous to smc_mclk0 | |
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smc_address_mask0_0[7:0] | Input | Address mask for chip select 0 | ||
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smc_address_match0_0[7:0] | Input | Address match for chip select 0 | ||
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smc_address_mask0_1[7:0] | Input | Address mask for chip select 1 | ||
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smc_address_match0_1[7:0] | Input | Address match for chip select 1 | ||
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smc_address_mask0_2[7:0] | Input | Address mask for chip select 2 | ||
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smc_address_match0_2[7:0] | Input | Address match for chip select 2 | ||
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smc_address_mask0_3[7:0] | Input | Address mask for chip select 3 | ||
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smc_address_match0_3[7:0] | Input | Address match for chip select 3 | ||
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smc_remap_0 | Input | Remap | ||
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smc_mux_mode_0 | Input | Multiplexor mode | ||
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smc_sram_mw_0[1:0] | Input | Memory width | ||
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smc_user_status[7:0] | Input | User signals to the configuration port | ||
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smc_user_config[7:0] | Output | System | User signals from the configuration port | |
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smc_int | Output | System | Interrupt | |
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Copyright © 2006 ARM Limited. All rights reserved. | ARM DDI 0389B |