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SMC Networks PL241, AHB SRAM/NOR manual SRAM memory accesses

Models: AHB SRAM/NOR PL241

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SRAM memory accesses

Functional Overview

The SMC ensures the ordering of read transfers from a single port is maintained RAR, and additionally that the ordering of write transfers from a single master is maintained WAW.

SRAM memory accesses

This section describes:

•Standard SRAM access

•Memory address shifting

•Memory burst alignment

•Memory burst length on page 2-21

•Booting using the SRAM on page 2-21.

Standard SRAM access

The programmer’s view is a flat area of memory.

The base addresses of external memory devices are defined by the

smc_address_match0_<0-3>[7:0 ] and smc_address_mask0_<0-3>[ 7:0] tie-off pins. You can read the values of these tie-off pins through the opmode registers.

Memory address shifting

To produce the address presented to the memory device, the AHB address is aligned to the memory width. This is done because the AHB address is a byte-aligned address, while the memory address is a memory-width-aligned address.

Note

During initial configuration of a memory device, the memory mode register can be accessed with a sequence of transfers to specific addresses. You must take into consideration the shifting performance by the SMC when accessing memory mode registers.

Memory burst alignment

The SMC provides a programmable option for controlling the formatting of memory transfers with respect to memory burst boundaries, through the burst_align bit of the opmode registers.

When set, the burst_align bit causes memory bursts to be aligned to a memory burst boundary. This setting is intended for use with memories that use the concept of internal pages. This can be an asynchronous page mode memory, or a synchronous PSRAM. If a burst crosses a memory burst boundary, the SMC partitions the transfer into multiple

2-20

Copyright © 2006 ARM Limited. All rights reserved.

ARM DDI 0389B

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SMC Networks PL241, AHB SRAM/NOR SRAM memory accesses, Standard SRAM access Memory address shifting Memory burst alignment

Contents

Technical Reference Manual PrimeCell AHB SRAM/NOR Memory Controller PL241Revision r0p1 PrimeCell AHB SRAM/NOR Memory Controller PL241 Technical Reference ManualRelease Information Proprietary NoticeContents PrefaceChapter IntroductionSignal Descriptions Programmer’s Model for TestDevice Driver Requirements Appendix AList of Tables Register summary List of Figures Synchronous burst read in multiplexed-mode Preface About this manual on pageFeedback on page Copyright 2006 ARM Limited. All rights reservedUsing this manual About this manualProduct revision status whereAppendix A Signal Descriptions Typographical Timing diagrams on pageConventions TypographicalTiming diagrams SignalsSignal level Denotes global Advanced eXtensible Interface AXI signalsDenotes Advanced High-performance Bus AHB signals Denotes Advanced Peripheral Bus APB signalsAMBA 3 APB Protocol v1.0 Specification ARM IHI Prefix BFeedback on this product FeedbackFeedback on this manual Chapter IntroductionAbout the AHB MC on page Supported devices on page Copyright 2006 ARM Limited. All rights reserved1.1 About the AHB MC Clock domains on page Low-power interfaces on pageAHB interface on page AHB to APB bridge on page 1.1.1 AHB interface 1.1.2 AHB to APB bridgePseudo Static Random Access Memory PSRAM 1.1.5 Low-power interfaces1.1.3 SMC 1.1.4 Clock domainsIntel W18 series NOR FLASH, for example 28f128W18td 1.2 Supported devicesCellular RAM 1.0, 64MB PSRAM, for example mt45w4mw16bfb7011us Copyright 2006 ARM Limited. All rights reserved IntroductionARM DDI 0389B Functional Overview Functional description on pageFunctional operation on page SMC functional operation on page ChapterLow-power interface on page 2.1 Functional descriptionAHB interface AHB to APB bridge Clock domains on page 2.1.1 AHB interfacesmcmreset0n 2.1.4 Low-power interface2.1.3 Clock domains AHB clock domain2.2 SMC SMC interface on page APB slave interface on pageMemory manager on page Memory interface on page Pad interface on page Figure 2-3 SMC block diagram2.2.1 SMC interface 2.2.2 APB slave interface2.2.3 Format 2.2.4 Memory manager2.2.6 Pad interface 2.2.7 InterruptsClock domain operation on page Low-power interface operation on page Broken bursts on page Bufferable bit of the HPROT signal on pageAHB response signals on page Locked transfers on page Removal of AHB error response logic on pageUndefined length INCR bursts Bufferable bit of the HPROT signalBroken bursts Read after write hazard detection buffer AHB response signalsLocked transfers Removal of AHB error response logic Registered HWDATABig-endian 32-bit mode 2.3.2 AHB to APB bridge operation2.3.3 Clock domain operation Figure 2-6 AHBC memory mapStatic memory clocking options 2.3.4 Low-power interface operationa request input domaincsyreq an acknowledge output domaincsysack an active output domaincactive Figure 2-9 Accepting requests Operating states Clocking and resets on page Miscellaneous signals on page APB slave interface operation on pageReset Power is applied to the device, and hresetn is held LOWReady to Reset Reset to ReadyReady to Low-power Low-power to ReadyResets AHB domainMemory clock domain Synchronous clocking2.4.3 Miscellaneous signals smcuserconfig70smcuserstatus70 smcagtm0syncHazard handling SRAM memory accesses on page smcmsync0smcrstbypass smcuseebiStandard SRAM access Memory address shifting Memory burst alignment SRAM memory accessesMemory burst length on page Booting using the SRAM on page Booting using the SRAM Memory burst lengthLow-power operation Chip configuration registers Direct commands on pageLow-power operation Chip configuration registersFigure 2-11 Chip configuration registers DSEBLIPHPFBFIJ VHWF\FOHV VHWRSPRGH FKLSF\FOHV FKLSRSPRGHDevice pin mechanism Direct commandsSoftware mechanism Figure 2-12 Device pin mechanism Functional Overview6WDUW ULWHWLPLQJSDUDPHWHUV DQGRSHUDWLQJPRGHWR WKHPHPRU\FRQWUROOHU KROGLQJUHJLVWHUV ULWHUHTXLUHGHWHUQDOFKLSFigure 2-13 Software mechanism Functional OverviewCopyright 2006 ARM Limited. All rights reserved ARM DDI 0389BThey are divided into SRAM timing tables and diagrams SRAM timing tables and diagrams2.4.7 Interrupts operation 2.4.8 Memory interface operationAsynchronous read Asynchronous read in multiplexed-mode on page Asynchronous write on pageAsynchronous write in multiplexed-mode on page Asynchronous page mode read on page Synchronous burst read on pageAsynchronous read in multiplexed-mode Figure 2-14 Asynchronous readFigure 2-15 Asynchronous read in multiplexed-mode smcdataout0310 output bus. Read data is accepted on the smcdatain0310 Table 2-10 Page read opmode chip register settings Asynchronous write in multiplexed-modeFigure 2-17 Asynchronous write in multiplexed-mode Asynchronous page mode readMultiplexed-mode page accesses are not supported Figure 2-19 Synchronous burst read Figure 2-20 Synchronous burst read in multiplexed-mode Table 2-16 Synchronous burst write opmode chip register settings Table 2-17 Synchronous burst write SRAM cycles register settingsSynchronous burst write Figure 2-21 Synchronous burst writeFigure 2-22 Synchronous burst write in multiplexed-mode Reads followed by writes Writes followed by reads For tRC For tWC Functional Overview Copyright 2006 ARM Limited. All rights reservedARM DDI 0389B 2-40Programmer’s Model About the programmer’s model on page Register summary on pageRegister descriptions on page ChapterSMC configuration registers SMC chip select configuration registersSMC user configuration registers 3.1 About the programmer’s model3.2 Register summary Figure 3-2 SMC configuration register mapFigure 3-3 SMC chip configuration register map Programmer’s ModelFigure 3-4 SMC user configuration register map Reset valueName Base offsetReset value Table 3-1 Register summary continuedName Base offset3.3 Register descriptions 3.3.1 SMC Memory Controller Status Register at3.3.2 SMC Memory Interface Configuration Register at Figure 3-7 smcmemifcfg Register bit assignmentsTable 3-3 smcmemifcfg Register bit assignments Bits3.3.3 SMC Set Configuration Register at Table 3-3 smcmemifcfg Register bit assignments continued3.3.4 SMC Clear Configuration Register at 0x100C BitsName Function3.3.5 SMC Direct Command Register at 3.3.6 SMC Set Cycles Register at 3.3.7 SMC Set Opmode Register at Figure 3-12 smcsetopmode Register bit assignmentsTable 3-8 lists the register bit assignments BitsName FunctionConfiguration Register at 0x1004 on page Table 3-8 smcsetopmode Register bit assignments continuedBits Name3.3.8 SMC Refresh Period 0 Register at 3.3.9 SMC SRAM Cycles Registers 0-3 at 0x1100, 0x1120, 0x11403.3.10 SMC Opmode Registers 0-3 at 0x1104, 0x1124, 0x1144 Table 3-11 lists the register bit assignments BitsName Function3.3.11 SMC User Status Register at Table 3-12 lists the register bit assignmentsTable 3-11 smcopmode Register bit assignments continued BitsTable 3-13 lists the register bit assignments 3.3.12 SMC User Configuration Register at3.3.13 SMC Peripheral Identification Registers 0-3 at 0x1FE0-0x1FEC SMC Peripheral Identification Register SMC Peripheral Identification Register 1 on pageSMC Peripheral Identification Register 2 on page SMC Peripheral Identification Register 3 on pageSMC Peripheral Identification Register SMC Peripheral Identification RegisterSMC Peripheral Identification Register Table 3-18 smcperiphid3 Register bit assignments3.3.14 SMC PrimeCell Identification Registers 0-3 at 0x1FF0-0x1FFC SMC PrimeCell Identification Register SMC PrimeCell Identification Register 2 on pageSMC PrimeCell Identification Register 3 on page SMC PrimeCell Identification RegisterThe smcpcellid2 Register is hard-coded and the fields within the register indicate the value. Table 3-22 lists the register bit assignments SMC PrimeCell Identification RegisterSMC PrimeCell Identification Register Programmer’s Model for Test SMC integration test registers on pageChapter Copyright 2006 ARM Limited. All rights reserved4.1.1 SMC Integration Configuration Register at 0x1E00 4.1 SMC integration test registers4.1.2 Integration Inputs Register at 0x1E044.1.3 Integration Outputs Register at 0x1E08 Table 4-3 smcintinputs Register bit assignments continuedBits NameDevice Driver Requirements Memory initialization on pageChapter Copyright 2006 ARM Limited. All rights reserved5.1 Memory initialization Figure 5-1 SMC and memory initialization sheet 1 of 6WDUW QLWLDOLHYDULDEOHV ULWHWLPLQJLQIRUPDWLRQ WRVPFBVHWBF\FOHVKROGLQJ5HJLVWHU ULWHRSHUDWLQJPRGH LQIRUPDWLRQWR VPFBVHWBRSPRGH KROGLQJ5HJLVWHUFigure 5-2 SMC and memory initialization sheet 2 of Device Driver Requirements6KHHW V PHPRU\GHYLFH 0RGH5HJDFFHVVHGE\ RUDGGUHVV RQO\Figure 5-3 SMC and memory initialization sheet 3 of Device Driver Requirements6KHHW 9HULI\ WKHQHZWLPLQJV DQGRSHUDWLQJ PRGH HV KHFNIRUFRUUHFW VPFBVUDPBF\FOHVB 5HJLVWHUFRQWHQWVCopyright 2006 ARM Limited. All rights reserved Device Driver RequirementsARM DDI 0389B Signal Descriptions About the signals list on page A-2 Clocks and resets on page A-3AHB signals on page A-4 SMC memory interface signals on page A-5 SMC miscellaneous signals on page A-6 Low-power interface on page A-7A.1 About the signals list Figure A-1 AHB MC PL241 grouping of signalsSignal Descriptions ORFNVA.2 Clocks and resets NameType SourceAHB signals Table A-2 AHB signalsName TypeA.4 SMC memory interface signals Table A-3 SMC memory interface signalsName TypeA.5 SMC miscellaneous signals Table A-4 SMC miscellaneous signalsName TypeA.6 Low-power interface NameType SourceA.7 Configuration signal Table A-6 Configuration signalSignal Descriptions NameA.8 Scan chains Table A-7 Scan chain signalsName TypeSignal Descriptions A-10Copyright 2006 ARM Limited. All rights reserved ARM DDI 0389BGlossary See Advanced High-performance Bus See Advanced Microcontroller Bus ArchitectureSee Advanced Peripheral Bus comprises four beatsSee also Beat incrementedto enable you to access selected parts of the device See Should Be OneSee Should Be Zero See Should Be Zero or Preservedhas been completed Glossary Glossary-6Copyright 2006 ARM Limited. All rights reserved ARM DDI 0389B