SMC Set Configuration Register at | SMC Networks PL241 specs

Programmer’s Model

			Table 3-3 smc_memif_cfg Register bit assignments (continued)

Bits	Name	Function

[3:2]	memory_chips0	Returns the number of different chip selects that the memory interface 0 supports:
		b00	= 1 chip
		b01	= 2 chips
		b10	= 3 chips
		b11	= 4 chips.

[1:0]	memory_type0	Returns the memory interface 0 type:
		b00	= reserved
		b01	= SRAM
		b10	= NAND
		b11	= reserved.

3.3.3SMC Set Configuration Register at 0x1008

The write-only smc_memc_cfg_set Register enables the memory controller to be changed to Low-power state, and interrupts enabled. This register cannot be written to in the Reset state. Figure 3-8shows the register bit assignments.

8QGHILQHG

ORZBSRZHUBUHT 5HVHUYHG LQWBHQDEOH

Figure 3-8 smc_memc_cfg_set Register bit assignments

3-8

Copyright © 2006 ARM Limited. All rights reserved.

ARM DDI 0389B

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SMC Networks PL241, AHB SRAM/NOR manual SMC Set Configuration Register at, Smcmemccfgset Register bit assignments

Contents

PrimeCell AHB SRAM/NOR Memory Controller PL241 Copyright 2006 ARM Limited. All rights reserved PrimeCell AHB SRAM/NOR Memory Controller PL241Technical Reference Manual Contents Chapter Programmer’s Model for Test List of Tables List of Tables List of Figures Figure A-1 AHB MC PL241 grouping of signals Preface Feedback on Using this manual About this manualProduct revision status Intended audience Bold ConventionsTypographical Timing diagrams Signals ARM publications NumberingFurther reading Feedback on this manual FeedbackFeedback on this product Introduction SMC on About the AHB MCThis section describes AHB interface AHB to APB bridge Clock domains Low-power interfaces3 SMC Supported devices Intel W18 series NOR FLASH, for example 28f128W18td Introduction Copyright 2006 ARM Limited. All rights reserved Functional Overview Functional description This section is divided into Smcmreset0n Low-power interfaceAHB clock domain Static memory clock domain SMC Main blocks of the SMC areFormat on Interrupts on SMC interface APB slave interfaceFormat Memory manager Pad interface Interrupts AHB fixed burst types Functional operationAHB interface operation Broken bursts Bufferable bit of the Hprot signalUndefined length Incr bursts Locked transfers AHB response signalsRead after write hazard detection buffer Big-endian 32-bit mode Removal of AHB error response logicRegistered Hwdata AHB to APB bridge operation Clock domain operation Ahbc memory map Low-power interface operation Static memory clocking options1lists the static memory clocking options Static memory clocking options Where Domain is ahb or smc An active output Domaincactive Accepting requests SMC states are as follows SMC functional operationOperating states Clocking and resets Clocking Resets Miscellaneous signals Smcuserconfig70Smcuserstatus70 Smcagtm0sync Hazard handling APB slave interface operationFormat block Sram memory accesses Memory burst length Memory manager operation Low-power operationChip configuration registers 11 Chip configuration registers Software mechanism Direct commandsDevice pin mechanism 12 Device pin mechanism 13 Software mechanism Memory interface operation Sram timing tables and diagramsInterrupts operation Asynchronous read opmode chip register settings Asynchronous read Sram cycles register settings 4and -5list the smcopmode00-3 and Sram Register settings 14 Asynchronous read Asynchronous write Sram cycles register settings 6and -7list the smcopmode00-3 and Sram Register settingsAsynchronous write opmode chip register settings 10 Page read opmode chip register settings 8and -9list the smcopmode00-3 and Sram Register settings10and -11list the smcopmode00-3 and Sram Register settings 13 Synchronous burst read Sram cycles register settings 12and -13list the smcopmode00-3 and Sram Register settings12 Synchronous burst read opmode chip register settings 19 Synchronous burst read 14and -15list the smcopmode00-3 and Sram Register settings 20 Synchronous burst read in multiplexed-mode 17 Synchronous burst write Sram cycles register settings 16and -17list the smcopmode00-3 and Sram Register settings16 Synchronous burst write opmode chip register settings 18and -19list the smcopmode00-3 and Sram Register settings 22 Synchronous burst write in multiplexed-mode 20and -21list the smcopmode00-3 and Sram Register settings B0100 B0110 B001 TCEOE is only required if wait is asserted when oen goes LOW TWC = ARM DDI 0389B Programmer’s Model About the programmer’s model 2shows the SMC configuration register map Register summary Name Base offset Type Reset value Description 1lists the SMC Registers Register summary Register descriptions This section describes the SMC registersSMC Memory Controller Status Register at 2lists the register bit assignments Bits Name Function SMC Memory Interface Configuration Register at3lists the register bit assignments SMC Set Configuration Register at Smcmemccfgset Register bit assignments SMC Clear Configuration Register at 0x100C 4lists the register bit assignments5lists the register bit assignments Smcmemccfgclr Register bit assignments Bits Name Function Smcdirectcmd Register bit assignments SMC Direct Command Register at6lists the register bit assignments SMC Set Cycles Register at Lists the register bit assignments SMC Set Opmode Register at 12 smcsetopmode Register bit assignments 8lists the register bit assignments Smcsetopmode Register bit assignments Memory width mw field Smcrefreshperiod0 Register bit assignments SMC Refresh Period 0 Register atSMC Sram Cycles Registers 0-3 at 0x1100, 0x1120, 0x1140 10lists the register bit assignments SMC Opmode Registers 0-3 at 0x1104, 0x1124, 0x1144 11lists the register bit assignments SMC User Status Register at 12lists the register bit assignments11 smcopmode Register bit assignments 12 smcuserstatus Register bit assignments SMC User Configuration Register at 13 smcuserconfig Register bit assignments13 lists the register bit assignments Bits Name Description 15 smcperiphid0 Register bit assignments Bits Name Function Following section describe the smcperiphid RegistersSMC Peripheral Identification Register 16 smcperiphid1 Register bit assignments Bits Name Function 17 smcperiphid2 Register bit assignments Bits Name Function SMC PrimeCell Identification Registers 0-3 at 0x1FF0-0x1FFC 19shows the register bit assignments These registers cannot be read in the Reset state Following sections describe the smcpcellid RegistersSMC PrimeCell Identification Register 20 smcpcellid0 Register bit assignments Bits Name Function 22 smcpcellid2 Register bit assignments Bits Name Function 23 smcpcellid3 Register bit assignments Bits Name Function Programmer’s Model for Test Test registers are provided for integration testing SMC Integration Configuration Register at 0x1E00SMC integration test registers Lists the SMC integration test registers Integration Inputs Register at 0x1E04 Smcintinputs Register bit assignments Bits Name Function Integration Outputs Register at 0x1E08 State Device Driver Requirements Memory initialization SMC and memory initialization sheet 1 SMC and memory initialization sheet 2 Where = denotes the appropriate chip select SMC and memory initialization sheet 3 ARM DDI 0389B Signal Descriptions About the signals list Where Ahbc = AHB Configuration signals Name Type Source Description Destination Clocks and resetsTable A-1lists the clock and reset signals AHB signals Table A-2lists the AHB signalsWhere = 0 or C, where C = Configuration Table A-2 AHB signals SMC memory interface signals Table A-3lists the SMC memory interface signals Table A-4 SMC miscellaneous signals SMC miscellaneous signalsTable A-4lists the SMC miscellaneous signals Low-power interface Table A-5lists the low-power interface signals Configuration signal Table A-6lists the configuration signalTable A-6 Configuration signal Name Source Description Type Destination Scan chains Table A-7lists the scan chain signalsTable A-7 Scan chain signals ARM DDI 0389B Advanced High-performance Bus AHB Advanced Microcontroller Bus Architecture Amba See also Little-endian memory Advanced Peripheral Bus APB Incremented An 8-bit data itemData bus Multi-master operation Divisible by four See UnpredictableThat event resource is Unpredictable Other purposes Has been completed Written as 0 and read asRemapping Reserved Glossary-6