Incremented, An 8-bit data item | SMC Networks AHB SRAM/NOR, PL241

Glossary

Boundary scan chain

	A boundary scan chain is made up of serially-connected devices that implement
	boundary scan technology using a standard JTAG TAP interface. Each device contains
	at least one TAP controller containing shift registers that form the chain connected
	between TDI and TDO, through which test data is shifted. Processors can contain
	several shift registers to enable you to access selected parts of the device.
Burst	A group of transfers to consecutive addresses. Because the addresses are consecutive,
	there is no requirement to supply an address for any of the transfers after the first one.
	This increases the speed at which the group of transfers can occur. Bursts over AMBA
	are controlled using signals to indicate the length of the burst and how the addresses are
	incremented.
	See also Beat.
Byte	An 8-bit data item.
Byte lane strobe	A signal that is used for unaligned or mixed-endian data accesses to determine the byte
	lanes that are active in a transfer. One bit of this signal corresponds to eight bits of the
	data bus.
Multi-master AHB	Typically a shared, not multi-layer, AHB interconnect scheme. More than one master
	connects to a single AMBA AHB link. In this case, the bus is implemented with a set of
	full AMBA AHB master interfaces. Masters that use the AMBA AHB-Lite protocol
	must connect through a wrapper to supply full AMBA AHB master signals to support
	multi-master operation.
Endianness	Byte ordering. The scheme that determines the order that successive bytes of a data
	word are stored in memory. An aspect of the system’s memory mapping.
	See also Little-endian and Big-endian
Little-endian	Byte ordering scheme in which bytes of increasing significance in a data word are stored
	at increasing addresses in memory.
	See also Big-endian and Endianness.
Little-endian memory
	Memory in which:
	•	a byte or halfword at a word-aligned address is the least significant byte or
		halfword within the word at that address
	•	a byte at a halfword-aligned address is the least significant byte within the
		halfword at that address.

SMC Networks AHB SRAM/NOR manual Incremented, An 8-bit data item, Data bus, Multi-master operation

Models: AHB SRAM/NOR PL241

incremented.

See also Beat.

An 8-bit data item.

Byte lane strobe

data bus.

multi-master operation.

See also Little-endian and Big-endian

at increasing addresses in memory.

See also Big-endian and Endianness.

Memory in which:

halfword within the word at that address

halfword at that address.

See also Big-endian memory.

ARM DDI 0389B