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Introduction
1.2Supported devices
The SMC supports SRAM/NOR, see SMC on page
Some memory devices or series of memory devices have specific requirements:
Intel W18 series NOR FLASH, for example 28f128W18td
These devices, when in synchronous operation, use a WAIT pin. However
Therefore, W18 devices can only carry out
Read Status in asynchronous modes of operation.
Cellular RAM 1.0, 64MB PSRAM, for example mt45w4mw16bfb_701_1us
You can program these devices using a CRE pin or by software access. Whenever you program these devices through software access, using a sequence of two reads followed by two writes, ensure that the third access, that is, the first write is a CE# controlled write.
SMC only does WE# controlled writes. This is to simplify the design of the
SMC by having fewer timing registers and simpler timing controls.
Therefore, you can only program these devices by using the CRE pin method of access.
Note
Because the memory controller maps INCR transfers into INCR4 transfers, it does not support memory mapped FIFO components.
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