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| Appendix D: BIOS POST Checkpoint Codes | |
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Checkpoint | Beep Code | Description | |
Code | |||
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1Ch |
| Initialize interrupt controllers for some shut- | |
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| downs. | |
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20h | Verify that DRAM refresh is operating by | ||
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| polling the refresh bit in PORTB. | |
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22h | Reset the keyboard. | ||
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24h |
| Set | |
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28h | Using the table of configurations supplied | ||
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| by the specific chipset module, test each | |
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| DRAM configuration to see if that particular | |
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| configuration is valid. Then program the | |
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| chipset to its autosized configuration. | |
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| Before autosizing, disable all caches and all | |
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| shadow RAM. | |
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29h | Initialize the POST Memory Manager. | ||
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2Ah |
| Zero the first 512K of RAM. | |
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2Ch | Test 512K base address lines. | ||
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2Eh | Test first 512K of RAM. | ||
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2Fh |
| Initialize external cache before shadowing. | |
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32h |
| Compute CPU speed. | |
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33h |
| Initialize the Phoenix Dispatch Manager. | |
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34h | CMOS test. | ||
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36h |
| Vector to proper shutdown routine. | |
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38h |
| Shadow the system BIOS. |
3Ah | Autosize external cache and program cache |
| size for enabling later in POST. |
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