Acer Altos R710 manual Checkpoint, Beep Code, Description

188		Appendix D: BIOS POST Checkpoint Codes
Checkpoint	Beep Code	Description
Code
1Ch		Initialize interrupt controllers for some shut-
		downs.
20h	1-3-1-1	Verify that DRAM refresh is operating by
		polling the refresh bit in PORTB.
22h	1-3-1-3	Reset the keyboard.
24h		Set segment-register addressibility to 4 GB.
28h	1-3-3-1	Using the table of configurations supplied
		by the specific chipset module, test each
		DRAM configuration to see if that particular
		configuration is valid. Then program the
		chipset to its autosized configuration.
		Before autosizing, disable all caches and all
		shadow RAM.
29h	1-3-3-2	Initialize the POST Memory Manager.
2Ah		Zero the first 512K of RAM.
2Ch	1-3-4-1	Test 512K base address lines.
2Eh	1-3-4-3	Test first 512K of RAM.
2Fh		Initialize external cache before shadowing.
32h		Compute CPU speed.
33h		Initialize the Phoenix Dispatch Manager.
34h	1-4-2-1	CMOS test.
36h		Vector to proper shutdown routine.
38h		Shadow the system BIOS.

3Ah	Autosize external cache and program cache
	size for enabling later in POST.