![](/images/new-backgrounds/1306544/306544397x1.webp)
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Checkpoint | Beep Code | Description | ||
Code | ||||
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14h |
| Verify that the 8742 keyboard controller is | ||
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| responding. Send a | ||
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| the 8742 and wait for results. Also read the | ||
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| switch inputs from the 8742 and write the | ||
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| keyboard controller command byte. | ||
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16h | Verify that the ROM BIOS checksums to | |||
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| zero. | ||
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17h |
| Initialize external cache before autosizing | ||
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| memory. | ||
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18h |
| Initialize all three of the 8254 timers. Set the | ||
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| clock timer (0) to binary count, mode 3 | ||
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| (square wave mode), and read/write LSB | ||
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| then MSB. Initialize the clock timer to zero. | ||
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| Set the RAM refresh timer (1) to binary | ||
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| count, mode 2 (Rate Generator), and read/ | ||
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| write LSB only. Set the counter to 12H to | ||
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| generate the refresh at the proper rate. Set | ||
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| sound timer (2) to binary count, mode 3, | ||
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| and read/write LSB, then MSB. | ||
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1Ah |
| Initialize DMA command register with these | ||
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| settings: | ||
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| 1. Memory to memory disabled | ||
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| 2. | Channel 0 hold address disabled | |
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| 3. | Controller enabled | |
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| 4. | Normal timing | |
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| 5. | Fixed priority | |
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| 6. | Late write selection | |
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| 7. | DREQ sense active | |
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| 8. | DACK sense active low |
Initialize all 8 DMA channels with these settings:
1.Single mode
2.Address increment
3.Auto initialization disabled (channel 4 - Cascade)
4.Verify transfer