192 |
| Appendix D: BIOS POST Checkpoint Codes | |
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Checkpoint | Beep Code | Description | |
Code | |||
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68h |
| Enable external cache and CPU cache if | |
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| present. | |
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| Configure | |
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| sary. | |
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| NOTE: Hook routine must preserve DX, | |
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| which carries the cache size to the Display- | |
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| CacheSizeJ routine. | |
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69h |
| Initialize the handler for SMM. | |
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| |
6Ah |
| Display external cache size on the screen if it | |
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| is | |
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| NOTE: Hook routine must preserve DX, | |
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| which carries the cache size from the cache- | |
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| ConfigureJ routine. | |
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| |
6Bh |
| If CMOS is bad, load Custom Defaults from | |
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| flash into CMOS. If successful, reboot. | |
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| |
6Ch |
| Display shadow message. | |
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6Eh |
| Display the starting offset of the | |
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| posable segment of the BIOS. | |
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| |
70h |
| Check flags in CMOS and in the BIOS data | |
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| area for errors detected during POST. Dis- | |
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| play error messages on the screen. | |
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72h |
| Check status bits to see if configuration | |
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| problems were detected. If so, display error | |
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| messages on the screen. | |
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76h |
| Check status bits for | |
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| ures. Display error messages on the screen. | |
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| |
7Ch |
| Initialize the hardware interrupt vectors | |
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| from 08 to 0F and from 70h to 77h. Also set | |
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| the interrupt vectors from 60h to 66h to | |
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| zero. | |
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7Dh |
| Initialize Intelligent System Monitoring. | |
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