Chapter 5 Theory of Operation

Direct Digital Synthesis (DDS ASIC)

Direct Digital Synthesis (DDS ASIC)

Block 2 on block diagram page 129; Schematic on page 132.

The DDS ASIC, U206, controls the WA (waveform address) and MA (modulation address) busses. The waveform address is used by the waveform RAMs U404 and U405. The modulation data bus is used by the modulation RAM U205.

The DDS ASIC is comprised of several internal registers and addressing state machines. Instructions are written to the DDS ASIC by the main CPU via memory mapped control registers U108 and U202. When loading data into Waveform RAM or Modulation RAM, addresses on the WA and MA busses are incremented by ASIC U206. ASIC addresses are incremented by each rising edge of the TRIG line while writing data into these RAM. The state of the HOST_RQ* line controls whether the main CPU or the modulation RAM U205 is sourcing instructions to the DDS ASIC internal state machines. The Modulation RAM is loaded with frequency values and amplitude flatness correction values or AM modulation data for latch U309 and AM dac U313. Data multiplexer U217 and flip-flop U215 are used to preselect and synchronize the modulation sync source available to the SYNC output terminal multiplexer U604.

The external trigger input OGEXT is optically isolated by U213 and

applied to an input of trigger source multiplexer U214. The external 5 trigger input is used for triggering the start of a frequency sweep or

burst output and for externally gating the output signal on and off asynchronously. U214 selects one of seven trigger sources for use by U206 for initiating its internal program.

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Agilent Technologies 33120A manual Direct Digital Synthesis DDS Asic, Block 2 on block diagram page 129 Schematic on